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| NJU6854 -1- ver.2004-06-29 132common x 132rgb lcd driver for 65,536-color stn display general description package the NJU6854 is a 132common x 132rgb lcd driver for 65,536-color stn display. it contains common drivers, rgb drivers, a serial and a parallel mpu interface circuit, an internal lcd power supply, grayscale palettes and 278,784-bit display data ram. the segment drivers for rgb (red, green, blue) independently produce optimum 64 or 32 grayscales from a built-in grayscale palette, and the lsi achieves 65,536 colors (64 x 32 x 32). in addition, the NJU6854 operates with a low voltage of 1.7v and a low operating current, therefore it is ideally suited for battery-powered handheld applications. features 65,536-color stn lcd driver built-in lcd drivers : 132-common x 132rgb (396-segment drivers) built-in display data ram (ddram) : 278,784 bits for graphic display programmable display mode - 64 grayscales(green) - 32 grayscales(red, blue) 3 areas partial display 8-/16-bit parallel interface selectable 8-/16-bit bus length for display data selectable 3-/4-line serial interface selectable programmable duty ratio and bias ratio programmable internal voltage booster : maximum 6 times programmable contrast control : 128-step electronic volume register (evr) various useful instructions low operating current low logic voltage : 1.7v to 3.3v wide lcd voltage range : 5.0v to 18.0v c-mos technology slim chip for cog package : bump chip bump chip
NJU6854 - 2 - ver.2004-06-29 table of contents general description package........................................................................................... 1 features ....................................................................................................................... ............................ 1 pad location................................................................................................................... ......................... 4 pad coordinates................................................................................................................ .................... 6 block diagram .................................................................................................................. ................... 12 lcd power supply block diagram ............................................................................................... 13 terminal description ........................................................................................................... ............. 14 functional description ......................................................................................................... .......... 17 (1) mpu interface.................................................................................................................. .................. 17 (1-1) selection of parallel/serial interface mode.............................................................................. ......................................17 (1-2) selection of mpu mode.................................................................................................... .............................................17 (1-3) data recognition ......................................................................................................... ..................................................17 (1-4) selection of 3-/4-line serial interface mode............................................................................. ......................................17 (1-5) 4-line serial interface mode............................................................................................. ..............................................17 (1-6) 3-line serial interface mode............................................................................................. ..............................................18 (1-7) data write............................................................................................................... .......................................................19 (1-8) data read ................................................................................................................ .....................................................21 (1-9) selection of 8-/16-bit bus length (parallel interface mode) .............................................................. ............................22 (2) initial display line........................................................................................................... ................. 22 (3) ddram .......................................................................................................................... .......................... 23 (3-1) ddram address range...................................................................................................... ..........................................23 (3-2) window area for ddram access............................................................................................. .....................................23 (3-3) ddram access direction................................................................................................... ...........................................24 (3-4) segment shift direction.................................................................................................. ...............................................26 (3-5) block diagram of ddram and peripheral circuit............................................................................ ..............................26 (3-6) ddram mapping............................................................................................................ ...............................................27 (3-6-1) (rew, swap) = (0,0), shift1 = ?0?, shift0 = ?0?, vpc = "84h? (1/132 duty), fvc = "00h", hct = ?00h?, ssc1 and ssc2 = ?0?, en3ptl = ?0?.............................................................................................. ..................................27 (3-6-2) (rew, swap) = (0,0), shift1 = ?0?, shift0 = ?0?, vpc = "70h? (1/112 duty), fvc = "00h", hct = ?0ah?, ssc1 and ssc2 = ?0?, en3ptl = ?0?.............................................................................................. ..................................28 (3-7) the relationship among bit assignment, x address and segment driver ...................................................... ..............29 (4) pwm control.................................................................................................................... .................. 36 (5) frame rate control(frc) ........................................................................................................ ..... 36 (6) display timing generator....................................................................................................... ...... 36 (7) data latch circuit............................................................................................................. ............... 36 (8) common drivers and segment drivers .................................................................................. 37 (9) oscillator..................................................................................................................... ...................... 38 (10) lcd power supply ............................................................................................................... ............. 38 (10-1) voltage booster ......................................................................................................... ..................................................39 (10-2) electrical volume register (evr) ........................................................................................ ........................................39 (10-3) voltage converter....................................................................................................... .................................................40 (10-3-1) voltage regulator .............................................................................................................. ...............................40 (10-3-2) reference voltage generator .................................................................................................... .......................41 (10-3-3) lcd bias voltage generator..................................................................................................... ........................41 (10-4) external components for lcd power supply................................................................................ ..............................42 (10-5) power on/off............................................................................................................ ................................................45 (10-6) discharge circuit ....................................................................................................... ..................................................45 (10-7) reset function .......................................................................................................... ..................................................46 (11) instruction tables............................................................................................................. ............. 47 (12) instruction descriptions ....................................................................................................... ..... 51 (12-1) 8-bit access mode ....................................................................................................... ................................................51 (12-1-1) instruction register........................................................................................................... ................................51 NJU6854 -3- ver.2004-06-29 (12-1-2) auto-increment of instruction register address................................................................................. ...............52 (12-2) 16-bit access mode ...................................................................................................... ...............................................53 (12-2-1) instruction register........................................................................................................... ................................53 (12-2-2) auto increment of instruction register address................................................................................. ...............53 (12-3) oscillation control ..................................................................................................... ..................................................54 (12-4) display data assignment/ window area onoff/increment control............................................................ ...............54 (12-5) display line number ..................................................................................................... ..............................................55 (12-6) blank line number ....................................................................................................... ...............................................55 (12-7) x address ............................................................................................................... .....................................................56 (12-8) y address ............................................................................................................... .....................................................56 (12-9) window end x address .................................................................................................... ...........................................56 (12-10) window end y address ................................................................................................... ..........................................56 (12-11) display mode/grayscale mode ............................................................................................ ......................................56 (12-12) oscillating frequency adjustment/frequency dividing.................................................................... ..........................60 (12-13) header com ............................................................................................................. ................................................61 (12-14) initial display line................................................................................................... ...................................................61 (12-15) scan start com 1....................................................................................................... ...............................................62 (12-16) scan start com 2....................................................................................................... ...............................................62 (12-17) line number of partial display 1 ....................................................................................... ........................................62 (12-18) line number of partial display 2 ....................................................................................... ........................................62 (12-19) n-line inversion ....................................................................................................... .................................................62 (12-20) power control 1........................................................................................................ .................................................63 (12-21) electronic volume control .............................................................................................. ...........................................64 (12-22) display timing signal monitor/pbx palette .............................................................................. .................................64 (12-23) power control 2........................................................................................................ .................................................65 (12-24) booster level/amplifier gain ........................................................................................... ..........................................66 (12-25) voltage booster clock .................................................................................................. .............................................67 (12-26) display control ........................................................................................................ ..................................................68 (12-27) pwm control ............................................................................................................ .................................................69 (12-28) three partial display areas/ led driver control/rev bit................................................................ ..........................70 (12-29) discharge on/off....................................................................................................... .............................................72 (12-30) led driver data ........................................................................................................ ................................................72 (12-31) instruction table/address .............................................................................................. ............................................72 (12-32) scan start com 3....................................................................................................... ...............................................73 (12-33) line number of partial display 3 ....................................................................................... ........................................73 (12-34) grayscale palette (pa0~pa31, pb0~pb31, pc0~pc31) ....................................................................... ...................74 (13) partial display function....................................................................................................... ........ 89 (14) relationship between logical com number and physical common driver............. 90 (15) typical instruction sequences ................................................................................................ 95 absolute maximum ratings....................................................................................................... ...... 98 recommended operating conditions ......................................................................................... 98 dc characteristics............................................................................................................. ............... 99 ac characteristics............................................................................................................. ............. 101 (1) write operation (80-type mpu) .................................................................................................. ............ 101 (2) read operation (80-type mpu)................................................................................................... ........... 102 (3) write operation (68-type mpu) .................................................................................................. ............ 103 (4) read operation (68-type mpu)................................................................................................... ........... 104 (5) serial interface ............................................................................................................... ........................ 105 (6) display control timing......................................................................................................... .................... 106 (7) reset input timing ............................................................................................................. ..................... 107 input/output block diagram ..................................................................................................... .. 108 mpu connections................................................................................................................ ............... 110 NJU6854 - 4 - ver.2004-06-29 pad location dummy vssh vssh ldat lsck lreq lresb test sel68 ps vdda resb csb rs wrb rdb vdda vssa d0 d1 d2 d3 d4 d5 d6 vssa d8 d9 d10 d11 d12 d13 d14 d15 lp m flm osco osci vssl d7 vdda vssl vdd vdd vee vee vba vba vref vref vssh dummy comb65 comb64 comb63 comb62 comb61 comb60 comb59 comb32 comb31 comb30 comb29 comb28 comb27 comb26 dummy comb25 dummy comb24 comb23 comb1 comb0 dummy dummy segc131 segb131 sega131 segc130 segb130 sega130 segc67 segb67 sega67 segc66 segb66 sega66 sega0~segc131, coma0~coma25, comb0~comb25, dummy coma26~coma65, comb26~comb65, dummy cpu interface pads and other pads bump material : au (gold) 115 50 15 115 180 245 50 15 23 140 1 5 23 140 1 5 50 15, 40, 65, 115, 120 NJU6854 -5- ver.2004-06-29 vssh vreg vreg vout vout c1p c1p c1n c1n c2p c2p c2n c2n c3p c3p c3n c3n c4p c4p c4n c4n c5p c5p c5n c5n v0 v0 v1 v1 v2 v2 v3 v3 v4 v4 vssh vssh dummy segc65 segb65 sega65 segc64 segb64 sega64 coma25 dummy coma24 coma23 coma1 coma0 dummy dummy segc1 segb1 sega1 segc0 segb0 sega0 dummy coma65 coma64 coma63 coma62 coma61 coma60 coma59 coma32 coma31 coma30 coma29 coma28 coma27 coma26 dummy note 1) the pads with the same name are connected within the chip. note 2) dummy pads are kept open.. unit: um size items remark / pad no. x y chip size with scribe lane (100 um) 17,643 2,180 driver pads pitch 38 pad pitch / space (bump) interface pads 70~170 driver sides 9 126 pad open side interface sides 9 96 driver sides 23 140 pad size (bump) interface sides 50 115 bump height all pads 17.5 align mark design bump metal only 25 50 50 50 25 25 25 metal only bump 25 50 50 50 25 25 25 pattern forbidden area left bottom align mark right bottom align mark coordinates left bottom : x= -8157.92 y= -515.62 right bottom : x= 8157.92 y= -515.62 NJU6854 - 6 - ver.2004-06-29 pad coordinates chip size 17,643 2,180 m 2 ( chip center = 0:0 ) pad no. pad name x( m) y( m) pad no. pad name x ( m) y ( m) pad no. pad name x ( m) y ( m) 1 dummy -8620.0 -935.5 51 d15 -3695.0 -935.5 101 vssha -20.0 -935.5 2 vssh -8530.0 -935.5 52 lp -3580.0 -935.5 102 vssha 45.0 -935.5 3 vssh -8465.0 -935.5 53 m -3465.0 -935.5 103 vssha 110.0 -935.5 4 vssh -8400.0 -935.5 54 flm -3350.0 -935.5 104 vssha 175.0 -935.5 5 vssh -8335.0 -935.5 55 osco -3235.0 -935.5 105 vreg 340.0 -935.5 6 vssh -8270.0 -935.5 56 osci -3120.0 -935.5 106 vreg 405.0 -935.5 7 vssh -8205.0 -935.5 57 vss -3005.0 -935.5 107 vreg 470.0 -935.5 8 vssh -8140.0 -935.5 58 vss -2940.0 -935.5 108 vreg 535.0 -935.5 9 vssh -8075.0 -935.5 59 vss -2875.0 -935.5 109 vreg 600.0 -935.5 10 vssh -8010.0 -935.5 60 vss -2810.0 -935.5 110 vout 690.0 -935.5 11 vssh -7945.0 -935.5 61 vss -2745.0 -935.5 111 vout 755.0 -935.5 12 vssh -7880.0 -935.5 62 vss -2680.0 -935.5 112 vout 820.0 -935.5 13 vssh -7815.0 -935.5 63 vss -2615.0 -935.5 113 vout 885.0 -935.5 14 vssh -7750.0 -935.5 64 vdd -2525.0 -935.5 114 vout 950.0 -935.5 15 vssh -7685.0 -935.5 65 vdd -2460.0 -935.5 115 vout 1015.0 -935.5 16 vssh -7620.0 -935.5 66 vdd -2395.0 -935.5 116 c1+ 1105.0 -935.5 17 vssh -7555.0 -935.5 67 vdd -2330.0 -935.5 117 c1+ 1170.0 -935.5 18 vssh -7490.0 -935.5 68 vdd -2265.0 -935.5 118 c1+ 1235.0 -935.5 19 ldat -7375.0 -935.5 69 vdd -2200.0 -935.5 119 c1+ 1300.0 -935.5 20 lsck -7260.0 -935.5 70 vee -2110.0 -935.5 120 c1+ 1365.0 -935.5 21 lreq -7145.0 -935.5 71 vee -2045.0 -935.5 121 c1+ 1430.0 -935.5 22 lresb -7030.0 -935.5 72 vee -1980.0 -935.5 122 c1- 1520.0 -935.5 23 test -6915.0 -935.5 73 vee -1915.0 -935.5 123 c1- 1585.0 -935.5 24 sel68 -6800.0 -935.5 74 vee -1850.0 -935.5 124 c1- 1650.0 -935.5 25 ps -6685.0 -935.5 75 vee -1785.0 -935.5 125 c1- 1715.0 -935.5 26 vdda -6570.0 -935.5 76 vee -1720.0 -935.5 126 c1- 1780.0 -935.5 27 resb -6455.0 -935.5 77 vee -1655.0 -935.5 127 c1- 1845.0 -935.5 28 csb -6340.0 -935.5 78 vee -1590.0 -935.5 128 c2+ 1935.0 -935.5 29 rs -6225.0 -935.5 79 vee -1525.0 -935.5 129 c2+ 2000.0 -935.5 30 wrb -6110.0 -935.5 80 vee -1460.0 -935.5 130 c2+ 2065.0 -935.5 31 rdb -5995.0 -935.5 81 vee -1395.0 -935.5 131 c2+ 2130.0 -935.5 32 vdda -5880.0 -935.5 82 vee -1330.0 -935.5 132 c2+ 2195.0 -935.5 33 vssa -5765.0 -935.5 83 vee -1265.0 -935.5 133 c2+ 2260.0 -935.5 34 d0 -5650.0 -935.5 84 vee -1200.0 -935.5 134 c2- 2350.0 -935.5 35 d1 -5535.0 -935.5 85 vba -1110.0 -935.5 135 c2- 2415.0 -935.5 36 d2 -5420.0 -935.5 86 vba -1045.0 -935.5 136 c2- 2480.0 -935.5 37 d3 -5305.0 -935.5 87 vba -980.0 -935.5 137 c2- 2545.0 -935.5 38 d4 -5190.0 -935.5 88 vba -915.0 -935.5 138 c2- 2610.0 -935.5 39 d5 -5075.0 -935.5 89 vba -850.0 -935.5 139 c2- 2675.0 -935.5 40 d6 -4960.0 -935.5 90 vref -760.0 -935.5 140 c3+ 2765.0 -935.5 41 d7 -4845.0 -935.5 91 vref -695.0 -935.5 141 c3+ 2830.0 -935.5 42 vdda -4730.0 -935.5 92 vref -630.0 -935.5 142 c3+ 2895.0 -935.5 43 vssa -4615.0 -935.5 93 vref -565.0 -935.5 143 c3+ 2960.0 -935.5 44 d8 -4500.0 -935.5 94 vref -500.0 -935.5 144 c3+ 3025.0 -935.5 45 d9 -4385.0 -935.5 95 vssha -410.0 -935.5 145 c3+ 3090.0 -935.5 46 d10 -4270.0 -935.5 96 vssha -345.0 -935.5 146 c3- 3180.0 -935.5 47 d11 -4155.0 -935.5 97 vssha -280.0 -935.5 147 c3- 3245.0 -935.5 48 d12 -4040.0 -935.5 98 vssha -215.0 -935.5 148 c3- 3310.0 -935.5 49 d13 -3925.0 -935.5 99 vssha -150.0 -935.5 149 c3- 3375.0 -935.5 50 d14 -3810.0 -935.5 100 vssha -85.0 -935.5 150 c3- 3440.0 -935.5 NJU6854 -7- ver.2004-06-29 chip size 17,643 2,180 m2 (chip center = 0:0 ) pad no. pad name x( m) y( m) pad no. pad name x ( m) y ( m) pad no. pad name x ( m) y ( m) 151 c3- 3505 -935.5 201 v4 7140 -935.5 251 coma39 8652 232 152 c4+ 3595 -935.5 202 v4 7205 -935.5 252 coma38 8652 270 153 c4+ 3660 -935.5 203 v4 7270 -935.5 253 coma37 8652 308 154 c4+ 3725 -935.5 204 v4 7335 -935.5 254 coma36 8652 346 155 c4+ 3790 -935.5 205 v4 7400 -935.5 255 coma35 8652 384 156 c4+ 3855 -935.5 206 vssh 7490 -935.5 256 coma34 8652 422 157 c4+ 3920 -935.5 207 vssh 7555 -935.5 257 coma33 8652 460 158 c4- 4010 -935.5 208 vssh 7620 -935.5 258 coma32 8652 498 159 c4- 4075 -935.5 209 vssh 7685 -935.5 259 coma31 8652 536 160 c4- 4140 -935.5 210 vssh 7750 -935.5 260 coma30 8652 574 161 c4- 4205 -935.5 211 vssh 7815 -935.5 261 coma29 8652 612 162 c4- 4270 -935.5 212 vssh 7880 -935.5 262 coma28 8652 650 163 c4- 4335 -935.5 213 vssh 7945 -935.5 263 coma27 8652 688 164 c5+ 4425 -935.5 214 vssh 8010 -935.5 264 coma26 8652 726 165 c5+ 4490 -935.5 215 vssh 8075 -935.5 265 dummy 8652 764 166 c5+ 4555 -935.5 216 vssh 8140 -935.5 266 dummy 8607 920.5 167 c5+ 4620 -935.5 217 vssh 8205 -935.5 267 coma25 8569 920.5 168 c5+ 4685 -935.5 218 vssh 8270 -935.5 268 coma24 8531 920.5 169 c5+ 4750 -935.5 219 vssh 8335 -935.5 269 coma23 8493 920.5 170 c5- 4840 -935.5 220 vssh 8400 -935.5 270 coma22 8455 920.5 171 c5- 4905 -935.5 221 vssh 8465 -935.5 271 coma21 8417 920.5 172 c5- 4970 -935.5 222 vssh 8530 -935.5 272 coma20 8379 920.5 173 c5- 5035 -935.5 223 dummy 8620 -935.5 273 coma19 8341 920.5 174 c5- 5100 -935.5 224 dummy 8652 -794 274 coma18 8303 920.5 175 c5- 5165 -935.5 225 coma65 8652 -756 275 coma17 8265 920.5 176 v0 5335 -935.5 226 coma64 8652 -718 276 coma16 8227 920.5 177 v0 5400 -935.5 227 coma63 8652 -680 277 coma15 8189 920.5 178 v0 5465 -935.5 228 coma62 8652 -642 278 coma14 8151 920.5 179 v0 5530 -935.5 229 coma61 8652 -604 279 coma13 8113 920.5 180 v0 5595 -935.5 230 coma60 8652 -566 280 coma12 8075 920.5 181 v0 5660 -935.5 231 coma59 8652 -528 281 coma11 8037 920.5 182 v1 5750 -935.5 232 coma58 8652 -490 282 coma10 7999 920.5 183 v1 5815 -935.5 233 coma57 8652 -452 283 coma9 7961 920.5 184 v1 5880 -935.5 234 coma56 8652 -414 284 coma8 7923 920.5 185 v1 5945 -935.5 235 coma55 8652 -376 285 coma7 7885 920.5 186 v1 6010 -935.5 236 coma54 8652 -338 286 coma6 7847 920.5 187 v1 6075 -935.5 237 coma53 8652 -300 287 coma5 7809 920.5 188 v2 6165 -935.5 238 coma52 8652 -262 288 coma4 7771 920.5 189 v2 6230 -935.5 239 coma51 8652 -224 289 coma3 7733 920.5 190 v2 6295 -935.5 240 coma50 8652 -186 290 coma2 7695 920.5 191 v2 6360 -935.5 241 coma49 8652 -148 291 coma1 7657 920.5 192 v2 6425 -935.5 242 coma48 8652 -110 292 coma0 7619 920.5 193 v2 6490 -935.5 243 coma47 8652 -72 293 dummy 7581 920.5 194 v3 6660 -935.5 244 coma46 8652 -34 294 dummy 7543 920.5 195 v3 6725 -935.5 245 coma45 8652 4 295 sega0 7505 920.5 196 v3 6790 -935.5 246 coma44 8652 42 296 segb0 7467 920.5 197 v3 6855 -935.5 247 coma43 8652 80 297 segc0 7429 920.5 198 v3 6920 -935.5 248 coma42 8652 118 298 sega1 7391 920.5 199 v3 6985 -935.5 249 coma41 8652 156 299 segb1 7353 920.5 200 v4 7075 -935.5 250 coma40 8652 194 300 segc1 7315 920.5 NJU6854 - 8 - ver.2004-06-29 chip size 17,643 2,180 m2 (chip center = 0:0 ) pad no. pad name x( m) y( m) pad no. pad name x ( m) y ( m) pad no. pad name x ( m) y ( m) 301 sega2 7277 920.5 351 segc18 5377 920.5 401 segb35 3477 920.5 302 segb2 7239 920.5 352 sega19 5339 920.5 402 segc35 3439 920.5 303 segc2 7201 920.5 353 segb19 5301 920.5 403 sega36 3401 920.5 304 sega3 7163 920.5 354 segc19 5263 920.5 404 segb36 3363 920.5 305 segb3 7125 920.5 355 sega20 5225 920.5 405 segc36 3325 920.5 306 segc3 7087 920.5 356 segb20 5187 920.5 406 sega37 3287 920.5 307 sega4 7049 920.5 357 segc20 5149 920.5 407 segb37 3249 920.5 308 segb4 7011 920.5 358 sega21 5111 920.5 408 segc37 3211 920.5 309 segc4 6973 920.5 359 segb21 5073 920.5 409 sega38 3173 920.5 310 sega5 6935 920.5 360 segc21 5035 920.5 410 segb38 3135 920.5 311 segb5 6897 920.5 361 sega22 4997 920.5 411 segc38 3097 920.5 312 segc5 6859 920.5 362 segb22 4959 920.5 412 sega39 3059 920.5 313 sega6 6821 920.5 363 segc22 4921 920.5 413 segb39 3021 920.5 314 segb6 6783 920.5 364 sega23 4883 920.5 414 segc39 2983 920.5 315 segc6 6745 920.5 365 segb23 4845 920.5 415 sega40 2945 920.5 316 sega7 6707 920.5 366 segc23 4807 920.5 416 segb40 2907 920.5 317 segb7 6669 920.5 367 sega24 4769 920.5 417 segc40 2869 920.5 318 segc7 6631 920.5 368 segb24 4731 920.5 418 sega41 2831 920.5 319 sega8 6593 920.5 369 segc24 4693 920.5 419 segb41 2793 920.5 320 segb8 6555 920.5 370 sega25 4655 920.5 420 segc41 2755 920.5 321 segc8 6517 920.5 371 segb25 4617 920.5 421 sega42 2717 920.5 322 sega9 6479 920.5 372 segc25 4579 920.5 422 segb42 2679 920.5 323 segb9 6441 920.5 373 sega26 4541 920.5 423 segc42 2641 920.5 324 segc9 6403 920.5 374 segb26 4503 920.5 424 sega43 2603 920.5 325 sega10 6365 920.5 375 segc26 4465 920.5 425 segb43 2565 920.5 326 segb10 6327 920.5 376 sega27 4427 920.5 426 segc43 2527 920.5 327 segc10 6289 920.5 377 segb27 4389 920.5 427 sega44 2489 920.5 328 sega11 6251 920.5 378 segc27 4351 920.5 428 segb44 2451 920.5 329 segb11 6213 920.5 379 sega28 4313 920.5 429 segc44 2413 920.5 330 segc11 6175 920.5 380 segb28 4275 920.5 430 sega45 2375 920.5 331 sega12 6137 920.5 381 segc28 4237 920.5 431 segb45 2337 920.5 332 segb12 6099 920.5 382 sega29 4199 920.5 432 segc45 2299 920.5 333 segc12 6061 920.5 383 segb29 4161 920.5 433 sega46 2261 920.5 334 sega13 6023 920.5 384 segc29 4123 920.5 434 segb46 2223 920.5 335 segb13 5985 920.5 385 sega30 4085 920.5 435 segc46 2185 920.5 336 segc13 5947 920.5 386 segb30 4047 920.5 436 sega47 2147 920.5 337 sega14 5909 920.5 387 segc30 4009 920.5 437 segb47 2109 920.5 338 segb14 5871 920.5 388 sega31 3971 920.5 438 segc47 2071 920.5 339 segc14 5833 920.5 389 segb31 3933 920.5 439 sega48 2033 920.5 340 sega15 5795 920.5 390 segc31 3895 920.5 440 segb48 1995 920.5 341 segb15 5757 920.5 391 sega32 3857 920.5 441 segc48 1957 920.5 342 segc15 5719 920.5 392 segb32 3819 920.5 442 sega49 1919 920.5 343 sega16 5681 920.5 393 segc32 3781 920.5 443 segb49 1881 920.5 344 segb16 5643 920.5 394 sega33 3743 920.5 444 segc49 1843 920.5 345 segc16 5605 920.5 395 segb33 3705 920.5 445 sega50 1805 920.5 346 sega17 5567 920.5 396 segc33 3667 920.5 446 segb50 1767 920.5 347 segb17 5529 920.5 397 sega34 3629 920.5 447 segc50 1729 920.5 348 segc17 5491 920.5 398 segb34 3591 920.5 448 sega51 1691 920.5 349 sega18 5453 920.5 399 segc34 3553 920.5 449 segb51 1653 920.5 350 segb18 5415 920.5 400 sega35 3515 920.5 450 segc51 1615 920.5 NJU6854 -9- ver.2004-06-29 chip size 17,643 2,180 m2 (chip center = 0:0 ) pad no. pad name x( m) y( m) pad no. pad name x ( m) y ( m) pad no. pad name x ( m) y ( m) 451 sega52 1577 920.5 501 segc68 -323 920.5 551 segb85 -2223 920.5 452 segb52 1539 920.5 502 sega69 -361 920.5 552 segc85 -2261 920.5 453 segc52 1501 920.5 503 segb69 -399 920.5 553 sega86 -2299 920.5 454 sega53 1463 920.5 504 segc69 -437 920.5 554 segb86 -2337 920.5 455 segb53 1425 920.5 505 sega70 -475 920.5 555 segc86 -2375 920.5 456 segc53 1387 920.5 506 segb70 -513 920.5 556 sega87 -2413 920.5 457 sega54 1349 920.5 507 segc70 -551 920.5 557 segb87 -2451 920.5 458 segb54 1311 920.5 508 sega71 -589 920.5 558 segc87 -2489 920.5 459 segc54 1273 920.5 509 segb71 -627 920.5 559 sega88 -2527 920.5 460 sega55 1235 920.5 510 segc71 -665 920.5 560 segb88 -2565 920.5 461 segb55 1197 920.5 511 sega72 -703 920.5 561 segc88 -2603 920.5 462 segc55 1159 920.5 512 segb72 -741 920.5 562 sega89 -2641 920.5 463 sega56 1121 920.5 513 segc72 -779 920.5 563 segb89 -2679 920.5 464 segb56 1083 920.5 514 sega73 -817 920.5 564 segc89 -2717 920.5 465 segc56 1045 920.5 515 segb73 -855 920.5 565 sega90 -2755 920.5 466 sega57 1007 920.5 516 segc73 -893 920.5 566 segb90 -2793 920.5 467 segb57 969 920.5 517 sega74 -931 920.5 567 segc90 -2831 920.5 468 segc57 931 920.5 518 segb74 -969 920.5 568 sega91 -2869 920.5 469 sega58 893 920.5 519 segc74 -1007 920.5 569 segb91 -2907 920.5 470 segb58 855 920.5 520 sega75 -1045 920.5 570 segc91 -2945 920.5 471 segc58 817 920.5 521 segb75 -1083 920.5 571 sega92 -2983 920.5 472 sega59 779 920.5 522 segc75 -1121 920.5 572 segb92 -3021 920.5 473 segb59 741 920.5 523 sega76 -1159 920.5 573 segc92 -3059 920.5 474 segc59 703 920.5 524 segb76 -1197 920.5 574 sega93 -3097 920.5 475 sega60 665 920.5 525 segc76 -1235 920.5 575 segb93 -3135 920.5 476 segb60 627 920.5 526 sega77 -1273 920.5 576 segc93 -3173 920.5 477 segc60 589 920.5 527 segb77 -1311 920.5 577 sega94 -3211 920.5 478 sega61 551 920.5 528 segc77 -1349 920.5 578 segb94 -3249 920.5 479 segb61 513 920.5 529 sega78 -1387 920.5 579 segc94 -3287 920.5 480 segc61 475 920.5 530 segb78 -1425 920.5 580 sega95 -3325 920.5 481 sega62 437 920.5 531 segc78 -1463 920.5 581 segb95 -3363 920.5 482 segb62 399 920.5 532 sega79 -1501 920.5 582 segc95 -3401 920.5 483 segc62 361 920.5 533 segb79 -1539 920.5 583 sega96 -3439 920.5 484 sega63 323 920.5 534 segc79 -1577 920.5 584 segb96 -3477 920.5 485 segb63 285 920.5 535 sega80 -1615 920.5 585 segc96 -3515 920.5 486 segc63 247 920.5 536 segb80 -1653 920.5 586 sega97 -3553 920.5 487 sega64 209 920.5 537 segc80 -1691 920.5 587 segb97 -3591 920.5 488 segb64 171 920.5 538 sega81 -1729 920.5 588 segc97 -3629 920.5 489 segc64 133 920.5 539 segb81 -1767 920.5 589 sega98 -3667 920.5 490 sega65 95 920.5 540 segc81 -1805 920.5 590 segb98 -3705 920.5 491 segb65 57 920.5 541 sega82 -1843 920.5 591 segc98 -3743 920.5 492 segc65 19 920.5 542 segb82 -1881 920.5 592 sega99 -3781 920.5 493 sega66 -19 920.5 543 segc82 -1919 920.5 593 segb99 -3819 920.5 494 segb66 -57 920.5 544 sega83 -1957 920.5 594 segc99 -3857 920.5 495 segc66 -95 920.5 545 segb83 -1995 920.5 595 sega100 -3895 920.5 496 sega67 -133 920.5 546 segc83 -2033 920.5 596 segb100 -3933 920.5 497 segb67 -171 920.5 547 sega84 -2071 920.5 597 segc100 -3971 920.5 498 segc67 -209 920.5 548 segb84 -2109 920.5 598 sega101 -4009 920.5 499 sega68 -247 920.5 549 segc84 -2147 920.5 599 segb101 -4047 920.5 500 segb68 -285 920.5 550 sega85 -2185 920.5 600 segc101 -4085 920.5 NJU6854 - 10 - ver.2004-06-29 chip size 17,643 2,180 m2 (chip center = 0:0 ) pad no. pad name x( m) y( m) pad no. pad name x ( m) y ( m) pad no. pad name x ( m) y ( m) 601 sega102 -4123 920.5 651 segc118 -6023 920.5 701 comb8 -7923 920.5 602 segb102 -4161 920.5 652 sega119 -6061 920.5 702 comb9 -7961 920.5 603 segc102 -4199 920.5 653 segb119 -6099 920.5 703 comb10 -7999 920.5 604 sega103 -4237 920.5 654 segc119 -6137 920.5 704 comb11 -8037 920.5 605 segb103 -4275 920.5 655 sega120 -6175 920.5 705 comb12 -8075 920.5 606 segc103 -4313 920.5 656 segb120 -6213 920.5 706 comb13 -8113 920.5 607 sega104 -4351 920.5 657 segc120 -6251 920.5 707 comb14 -8151 920.5 608 segb104 -4389 920.5 658 sega121 -6289 920.5 708 comb15 -8189 920.5 609 segc104 -4427 920.5 659 segb121 -6327 920.5 709 comb16 -8227 920.5 610 sega105 -4465 920.5 660 segc121 -6365 920.5 710 comb17 -8265 920.5 611 segb105 -4503 920.5 661 sega122 -6403 920.5 711 comb18 -8303 920.5 612 segc105 -4541 920.5 662 segb122 -6441 920.5 712 comb19 -8341 920.5 613 sega106 -4579 920.5 663 segc122 -6479 920.5 713 comb20 -8379 920.5 614 segb106 -4617 920.5 664 sega123 -6517 920.5 714 comb21 -8417 920.5 615 segc106 -4655 920.5 665 segb123 -6555 920.5 715 comb22 -8455 920.5 616 sega107 -4693 920.5 666 segc123 -6593 920.5 716 comb23 -8493 920.5 617 segb107 -4731 920.5 667 sega124 -6631 920.5 717 comb24 -8531 920.5 618 segc107 -4769 920.5 668 segb124 -6669 920.5 718 comb25 -8569 920.5 619 sega108 -4807 920.5 669 segc124 -6707 920.5 719 dummy -8607 920.5 620 segb108 -4845 920.5 670 sega125 -6745 920.5 720 dummy -8652 764 621 segc108 -4883 920.5 671 segb125 -6783 920.5 721 comb26 -8652 726 622 sega109 -4921 920.5 672 segc125 -6821 920.5 722 comb27 -8652 688 623 segb109 -4959 920.5 673 sega126 -6859 920.5 723 comb28 -8652 650 624 segc109 -4997 920.5 674 segb126 -6897 920.5 724 comb29 -8652 612 625 sega110 -5035 920.5 675 segc126 -6935 920.5 725 comb30 -8652 574 626 segb110 -5073 920.5 676 sega127 -6973 920.5 726 comb31 -8652 536 627 segc110 -5111 920.5 677 segb127 -7011 920.5 727 comb32 -8652 498 628 sega111 -5149 920.5 678 segc127 -7049 920.5 728 comb33 -8652 460 629 segb111 -5187 920.5 679 sega128 -7087 920.5 729 comb34 -8652 422 630 segc111 -5225 920.5 680 segb128 -7125 920.5 730 comb35 -8652 384 631 sega112 -5263 920.5 681 segc128 -7163 920.5 731 comb36 -8652 346 632 segb112 -5301 920.5 682 sega129 -7201 920.5 732 comb37 -8652 308 633 segc112 -5339 920.5 683 segb129 -7239 920.5 733 comb38 -8652 270 634 sega113 -5377 920.5 684 segc129 -7277 920.5 734 comb39 -8652 232 635 segb113 -5415 920.5 685 sega130 -7315 920.5 735 comb40 -8652 194 636 segc113 -5453 920.5 686 segb130 -7353 920.5 736 comb41 -8652 156 637 sega114 -5491 920.5 687 segc130 -7391 920.5 737 comb42 -8652 118 638 segb114 -5529 920.5 688 sega131 -7429 920.5 738 comb43 -8652 80 639 segc114 -5567 920.5 689 segb131 -7467 920.5 739 comb44 -8652 42 640 sega115 -5605 920.5 690 segc131 -7505 920.5 740 comb45 -8652 4 641 segb115 -5643 920.5 691 dummy -7543 920.5 741 comb46 -8652 -34 642 segc115 -5681 920.5 692 dummy -7581 920.5 742 comb47 -8652 -72 643 sega116 -5719 920.5 693 comb0 -7619 920.5 743 comb48 -8652 -110 644 segb116 -5757 920.5 694 comb1 -7657 920.5 744 comb49 -8652 -148 645 segc116 -5795 920.5 695 comb2 -7695 920.5 745 comb50 -8652 -186 646 sega117 -5833 920.5 696 comb3 -7733 920.5 746 comb51 -8652 -224 647 segb117 -5871 920.5 697 comb4 -7771 920.5 747 comb52 -8652 -262 648 segc117 -5909 920.5 698 comb5 -7809 920.5 748 comb53 -8652 -300 649 sega118 -5947 920.5 699 comb6 -7847 920.5 749 comb54 -8652 -338 650 segb118 -5985 920.5 700 comb7 -7885 920.5 750 comb55 -8652 -376 NJU6854 -11- ver.2004-06-29 chip size 17,643 2,180 m2 (chip center = 0:0 ) pad no. pad name x( m) y( m) pad no. pad name x ( m) y ( m) pad no. pad name x ( m) y ( m) 751 comb56 -8652 -414 752 comb57 -8652 -452 753 comb58 -8652 -490 754 comb59 -8652 -528 755 comb60 -8652 -566 756 comb61 -8652 -604 757 comb62 -8652 -642 758 comb63 -8652 -680 759 comb64 -8652 -718 760 comb65 -8652 -756 761 dummy -8652 -794 NJU6854 - 12 - ver.2004-06-29 block diagram grayscale control circuit vee vss vssh a v0 v1 v2 v3 v4 vout c1+ c1- c2+ c2- c3+ c3- c4+ c4- c5+ c5- vreg vref vba lp flm m osci osco test vdd vdda vssa vss voltage regulator generator display timing generator oscillator circuit instruction decoder data latch circuit mpu interface register control sel68 csb rs wrb ps resb rdb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4/spol d3/smode d2 d1/sd a d0/scl ldat lsc k lreq lresb register bus holder bus i/o buffer data manager ram interface x address register x address counter x address decoder duty manager display control lcd bias voltage generator voltage booster driver power grayscale palettes sega0 segb0 segc0 sega131 segb131 segc131 com a 0 coma65 comb0 comb65 segment driver common driver decoder driver control display data ram 132rgb x 132 278.784bit y address decoder y address counter y address register line address decoder line counter line address register 396 132 NJU6854 -13- ver.2004-06-29 lcd power supply block diagram note) when external v ref is used, keep reference voltage circuit open (vgoff=?0?, vbon=?0?). temp coefficient setting register v0 + - v1 + - v2 + - v3 + - v4 + - + - + - this point is 1/2 vreg vreg vref dc/dc booster c1+ c1- c2+ c2- c3+ c3- c4+ c4- c5+ c5- vee vout voltage converter step setting register vreg gain setting register electric volume register lcd bias setting register + - temperature bias circuit vba bg vee temp coefficient setting register v0 + - v1 + - v2 + - v3 + - v4 + - + - + - this point is 1/2 vreg vreg vref dc/dc booster c1+ c1- c2+ c2- c3+ c3- c4+ c4- c5+ c5- vee vout voltage converter step setting register vreg gain setting register electric volume register vreg vref dc/dc booster c1+ c1- c2+ c2- c3+ c3- c4+ c4- c5+ c5- vee vout voltage converter step setting register vreg gain setting register electric volume register lcd bias setting register + - temperature bias circuit vba bg vee NJU6854 - 14 - ver.2004-06-29 terminal description power supply no. te r m i n a l i/o description 64-69 v dd power power supply for logic circuits 26,32,42 v dda power v dda is internally connected to v dd to fix sel68 or p/s to ?h? if necessary, and cannot be used as main power supply. ? v dda should be open if not used 33,43 v ssa power v ssa is internally connected to v ss to fix sel68 or p/s to ?l? if necessary, and cannot be used as main gnd. ? v ssa should be open if not used. 57-63 v ss power gnd for logic circuits 95-104 v ssha power gnd for voltage converter circuits 206-222 v ssh power gnd for voltage booster 176-205 v 0 v 1 v 2 v 3 v 4 power/o lcd bias voltages ? when the internal lcd power supply is used, internal lcd bias voltages (v 0 -v 4 ) are activated by the ?power control? instruction. stabilizing capacitors are required between each bias voltage and v ss . ? when the external lcd power supply is used, lcd bias voltages are externally supplied on v 0 , v 1 , v 2 , v 3 and v 4 individually, with the following relation maintained: v ssh NJU6854 - 16 - ver.2004-06-29 lcd output no. te r m i n a l i/o description segment drivers output rev mode turn-off turn-on normal 0 1 reverse 1 0 295-690 sega 0 ~ sega 131 , segb 0 ~ segb 131 , segc 0 ~ segc 131 o m signal display ram data nomal mode reverse mode v2 vss v3 v0 v0 v2 vss v3 54 flm o normally open. 53 m normally open. 52 lp o normally open. 225-292 coma 0 ~ coma 65 comb 0 ~ comb 65 o common divers output data fr output level h h v ssh l h v 1 h l v 0 l l v 4 oscillator 56 osci i when using the internal resistor, connect osci to ?l? and keep osco open 55 osco o when using an external resistor, connect osci and osco with the external resistor, and if using external clock, input 50% duty signal into the osci. white led driver ports 19 ldat i/o white led control port: data input/output 20 lsck o white led control port: shift clock output 21 lreq o white led control port: data request output 22 lresb o white led control port: reset output NJU6854 -17- ver.2004-06-29 functional description (1) mpu interface (1-1) selection of parallel/serial interface mode the p/s selects a parallel or a serial interface mode, as shown in table 1. in the serial interface mode, neither display data in the ddram nor instruction data in the registers can be read out. table 1 selection of parallel/serial interface mode p/s i/f mode csb rs rdb wrb sel68 sda scl data h parallel i/f csb rs rdb wrb sel68 d 7 -d 0 (d 15 -d 0 ) l serial i/f csb rs - - - sda scl - note) ? -? : fix to ?h? or ?l?. (1-2) selection of mpu mode in the parallel interface mode, the sel68 selects 68 or 80-series mpu mode, as shown in table 2. table 2 selection of mpu mode sel68 mpu mode csb rs rdb wrb data h 68-series mpu csb rs e r/w d 7 -d 0 (d 15 -d 0 ) l 80-series mpu csb rs rdb wrb d 7 -d 0 (d 15 -d 0 ) (1-3) data recognition in the parallel interface mode, the data from mpu is interpreted as display data or instruction according to the combination of the rs, rdb and wrb (r/w) signals, as shown in table 3. table 3 data recognition (parallel interface mode) 68-series 80-series rs r/w rdb wrb function h h l h read instruction h l h l write instruction l h l h read display data l l h l write display data (1-4) selection of 3-/4-line serial interface mode in the serial interface mode, the smode selects 3- or 4-line serial interface mode, as shown in table 4. table 4 selection of 3-/4-line serial interface mode smode serial interface mode h 3-line l 4-line (1-5) 4-line serial interface mode while the chip select is active (csb=?l?), the sda and scl are enabled. while the chip select is inactive (csb=?h?), the sda and scl are disabled, and the internal shift register and the internal counter are being initialized. 8-bit serial data on the sda is latched at the rising edge of the scl signal in order of d 7 , d 6 ,?, and d 0 , and converted into 8-bit parallel data at the timing of the internal signal produced from the 8 th scl signal. the data on the sda is interpreted as display data or instruction according to the rs. table 5 data recognition (4-line serial interface) rs data recognition h instruction l display data NJU6854 - 18 - ver.2004-06-29 note that the scl should be set to ?l? right after data transmission or during non-access because the serial interface is susceptible to external noises which may cause malfunctions. for added safety, inactivate the chip-select (csb=?h?) temporary whenever 8-bit data transmission is completed. fig 1 illustrates the interface timing of the 4-line serial interface mode. fig 1 4-line serial interface timing (1-6) 3-line serial interface mode while the chip select is active (csb=?l?), the sda and scl are enabled. while the chip select is not active (csb=?h?), the sda and scl are disabled, and the internal shift register and the internal counter are being initialized. 9-bit serial data on the sda is latched at the rising edge of the scl signal in order of rs, d 7 , d 6 ,?, and d 0 , and then converted into 9-bit parallel data at the timing of the internal signal produced from the 9 th scl signal. the data on the sda is interpreted as display data or instruction according to the combination of the rs bit and the spol status, as follows. table 6 data recognition (3-line serial interface) spol=l spol=h rs data recognition rs data recognition 0 display data 0 instruction 1 instruction 1 display data note that the scl should be set to ?l? right after data transmission or during non-access because the serial interface is susceptible to external noises which may cause malfunctions. for added safety, inactivate the chip-select (csb=?h?) temporary whenever 9-bit data transmission is completed. fig 2 illustrates the interface timing of the 3-line serial interface mode. fig 2 3-line serial interface timing rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 1 2 3 4 5 6 7 8 csb sda scl d 0 9 d 7 d 6 d 5 d 4 d 3 d 2 d 1 valid 1 2 3 4 5 6 7 8 csb rs sda scl d 0 NJU6854 -19- ver.2004-06-29 (1-7) data write while the chip select is active (csb=?l?), the data from mpu can be written into the ddram or the instruction register. when the rs is ?l?, the data is interpreted as display data which is stored in the ddram. the display data is latched at the rising edge of the wrb signal in the 80-series mpu mode, or at the falling edge of the e signal in the 68-series mpu mode. table 7 data recognition rs data recognition l display data h instruction 8-bit access to ddram 8-bit access to instruction register fig 3 data write operations in 8-bit accessing to instruction register accessing to ddram d0~d7 wrb rs data0 data1 data2 data3 d0~d7 msb=0/table address /register address data datat 0 1 st access 1 st access msb=1/table address /counter number data datat 0 datat n-1 wrb rs data datat 0 1 st access 1 st access data n-1 d0~d7 msb=0/table address /register address data datat 0 1 st access 1 st access msb=1/table address /counter number data datat 0 datat n-1 wrb rs data datat 0 1 st access 1 st access data n-1 NJU6854 - 20 - ver.2004-06-29 16-bit access to ddram 16-bit access to instruction register fig 4 data write operations in 16-bit accessing to instruction register accessing to ddram d8~d15 d0~d7 rs data0 data1 data2 data3 data0 data1 data2 data3 accessing to instruction register accessing to ddram d8~d15 d0~d7 wrb rs data0 data1 data2 data3 data0 data1 data2 data3 accessing to instruction register accessing to ddram d8~d15 d0~d7 rs data0 data1 data2 data3 data0 data1 data2 data3 accessing to instruction register accessing to ddram d8~d15 d0~d7 wrb rs data0 data1 data2 data3 data0 data1 data2 data3 data0 data1 data2 data3 data1 op code invalid msb=0/table address/register address msb=0/table address/register address msb=1/table address/counter number(n) d8~d15 d0~d7 wrb rs op code op code data0 datan-2 data0 data0 datan-2 data1 op code invalid msb=0/table address/register address msb=0/table address/register address msb=1/table address/counter number(n) d8~d15 d0~d7 rs op code op code data0 datan-2 data0 data0 datan-2 data1 op code invalid msb=0/table address/register address msb=0/table address/register address msb=1/table address/counter number(n) d8~d15 d0~d7 wrb rs op code op code data0 datan-2 data0 data0 datan-2 data1 op code invalid msb=0/table address/register address msb=0/table address/register address msb=1/table address/counter number(n) d8~d15 d0~d7 rs op code op code data0 datan-2 data0 data0 datan-2 NJU6854 -21- ver.2004-06-29 (1-8) data read just after address setting or data write operation, make sure to conduct dummy read operation once. the reason lies below, data from cpu is temporarily held in the built-in bus holder, and then released to the internal data bus, therefore a dummy data will be read out by the 1 st ?display data read? instruction, the wanted data will be read out by the 2 nd instruction. display data read in 8-bit display data read in 16-bit instruction data read in 8-bit instruction data read in 16-bit fig 5 data read operations rdb d 0 ~d 7 rs address set(ax,ay) address= n wrb dummy read op code address= n address= n+1 rdb d~d 7 rs address set(ax,ay) address= n dummy read op code address= n address= n+1 rdb d 0 ~d 7 rs address set(ax,ay) address= n dummy read op code address= n address= n+1 d~d 7 rs address set(ax,ay) address= n dummy read op code address= n address= n+1 rdb d 0 ~d 7 rs address set(ax,ay) address= n wrb dummy read op code address= n address= n+1 rdb d~d 7 rs address set(ax,ay) address= n dummy read op code address= n address= n+1 rdb d 0 ~d 7 rs address set(ax,ay) address= n dummy read op code address= n address= n+1 d~d 7 rs address set(ax,ay) address= n dummy read op code address= n address= n+1 op code address= n address= n+1 rdb d 0 ~d 7 rs address set(ax,ay) address=n wrb dummy read d 8 ~d 15 op code dummy read n data read address = n n n+1 data read address = n+1 n+1 n+2 data read address = n+2 n+2 d 0 ~d 7 rs address set(ax,ay) address=n dummy read d~d 15 n n n+1 n+1 n+2 n+2 d 0 ~d 7 rs address set(ax,ay) address=n dummy read d 8 ~d 15 op code dummy read rdb d 0 ~d 7 rs address set(ax,ay) address=n wrb dummy read d 8 ~d 15 op code dummy read n data read address = n n n+1 data read address = n+1 n+1 n+2 data read address = n+2 n+2 d 0 ~d 7 rs address set(ax,ay) address=n dummy read d~d 15 n n n+1 n+1 n+2 n+2 d 0 ~d 7 rs address set(ax,ay) address=n dummy read d 8 ~d 15 op code dummy read rdb address wrb rs set ? ra ? instruction table address /register address data read d0~d7 data 1d h address rs set ? ra ? instruction table address /register address data read d0~d7 data 1d h rdb address wrb rs set ? ra ? instruction table address /register address data read d0~d7 data 1d h address rs set ? ra ? instruction table address /register address data read d0~d7 data 1d h rdb d 0 ~d 7 address rs wrb d 8 ~d 15 1d h data address 1d h invalid invalid d 0 ~d 7 address rs d 8 ~d 15 1d h data data read address invalid invalid table address / register address set ? ra ? instruction data d 0 ~d 7 address rs d 8 ~d 15 1d h data address 1d h d~d 7 address rs d 8 ~d 15 1d h data address 1d h rdb d 0 ~d 7 address rs wrb d 8 ~d 15 1d h data address 1d h invalid invalid d 0 ~d 7 address rs d 8 ~d 15 1d h data data read address invalid invalid table address / register address set ? ra ? instruction data d 0 ~d 7 address rs d 8 ~d 15 1d h data address 1d h d~d 7 address rs d 8 ~d 15 1d h data address 1d h NJU6854 - 22 - ver.2004-06-29 (1-9) selection of 8-/16-bit bus length (parallel interface mode) either 8- or 16-bit bus length can be selected by the d 0 (swif) bit of the cfg register. swif = ?0? : 8-bit bus d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z swif = ?1? : 16-bit bus d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 11 d 12 d 13 d 14 d 15 bit assignment is determined by the d 1 (uds) bit of the cfg register. 16-bit access uds = ?0? internal bus d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 11 d 12 d 13 d 14 d 15 io pad d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 11 d 12 d 13 d 14 d 15 uds = ?1? internal bus d 8 d 9 d 10 d 11 d 12 d 13 d 14 d 15 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 io pad d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 11 d 12 d 13 d 14 d 15 8-bit access uds = ?0? internal bus d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 11 d 12 d 13 d 14 d 15 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 io pad d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 1 st access io pad 2 nd access d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 uds = ?1? internal bus d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 11 d 12 d 13 d 14 d 15 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 io pad 1 st access d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 io pad d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 2 nd access during 8-bit access, d15~d8 pins become high impedance, make sure fix them to h? or ?l?. (2) initial display line the initial display line register(hst) specifies a ddram y address, and display data corresponding to this address will be displayed by the scan start com 1. the y address specified by the initial display line register is preset into the line counter whenever the flm becomes ?h?. at the rising edge of the lp signal, the line counter is counted-up, then display data is latched into the data latch circuit. at the falling edge of the lp signal, the latch data is released to the grayscale control circuit to decide a grayscale level, then the segment drivers ai, bi and ci (i=0 to 131) generate lcd waveforms. NJU6854 -23- ver.2004-06-29 (3) ddram (3-1) ddram address range the ddram is capable of 132 bits for y address and 2,112 bits (16-bit x 132-segment) for x address. the x and y address are from 00 h to 83 h . address setting outside these ranges is not allowed, otherwise it may cause malfunctions. when auto-increment(auto-decrement) function is used during ddram access, y address and/or x address will be automatically increased(decreased). this operation is independent from line counter count-up (count-down). x-address 0 h 83 h 0 h 16bit 16bit y-address 83 h 16bit 16bit (3-2) window area for ddram access besides the normal ddram access discussed previously, it is possible to access only a specified window area by using cfg, adrh, adrl, eadrh and eadrl registers to define a start point and an end point. when auto-increment(auto-decrement) function enabled, y address and/or x address will be automatically increased(decreased) whenever ddram is accessed. and, the start point is specified by the x address register (adrh) and y address register(adrl), the end point by the window end x address register(eadrh) and window end y address register(eadrl). for the details, refer to the instruction table. the typical sequence of the window area setting is listed below. 1. set d 7 (aim1), d 6 (aim0), d 5 (vwr), d 4 (idsy), d 3 (idsx), and d 2 (win) bit of cfg register. 2. set start point by adrh and adrl register. 3. set end point by eadrh and eadrl register. 4. window area is set up, and ddram can be accessed. x address start point (x, y) end point y address window area (x, y) ddram area note1) the following relationship should be maintained to avoid malfunctions. - ax (window start x address) < ex (window end x address) < maximum x address - ay (window start y address) < ey (window end y address) < maximum y address note2) auto-increment in the window area note3) when aim[1:0]=(0,1), read-modify-write operation is valid. column address row address start ad d r e s s end ad d r e s s start address end address NJU6854 - 24 - ver.2004-06-29 (3-3) ddram access direction registers setting adrh eadrh adrl eadrl win aim idsx idsy vwr dddram access direction remark 00,00 01,00 83,00 00 x 00 x 0 00 0 0 0 (h) (h) (h) (h) 00,83 83,83 00,00 82,00 83,00 83 x 00 x 0 00 1 0 0 (h) (h) (h) (h) 00,83 83,83 00,00 83,00 00 x 83 x 0 00 0 1 0 (h) (h) (h) (h) 00,83 01,83 83,83 00,00 83,00 83 x 83 x 0 00 1 1 0 (h) (h) (h) (h) 00,83 82,83 83,83 window area 06,10 07,10 7d,10 06 7d 10 6a 1 00 0 0 0 (h) (h) (h) (h) 06,6a 7d,6a window area 06,10 7c,10 7d,10 7d 06 10 6a 1 00 1 0 0 (h) (h) (h) (h) 06,6a 7d,6a window area 06,10 7d,10 06 7d 6a 10 1 00 0 1 0 (h) (h) (h) (h) 06,6a 07,6a 7d,6a window area 06,10 7d,10 7d 06 6a 10 1 00 1 1 0 (h) (h) (h) (h) 06,6a 7c,6a 7d,6a NJU6854 -25- ver.2004-06-29 registers setting adrh eadrh adrl eadrl win aim idsx idsy vwr dddram access direction remark 00,00 83,00 00,01 00 x 00 x 0 00 0 0 1 (h) (h) (h) (h) 00,83 83,83 00,00 83,00 83,01 83 x 00 x 0 00 1 0 1 (h) (h) (h) (h) 00,83 83,83 00,00 83,00 00 x 83 x 0 00 0 1 1 (h) (h) (h) (h) 00,82 00,83 83,83 00,00 83,00 83 x 83 x 0 00 1 1 1 (h) (h) (h) (h) 83,82 00,83 83,83 window area 06,10 7d,10 06 7d 10 6a 1 00 0 0 1 06,11 (h) (h) (h) (h) 06,6a 7d,6a window area 06,10 7d,10 7d 06 10 6a 1 00 1 0 1 7d,11 (h) (h) (h) (h) 06,6a 7d,6a window area 06,10 7d,10 06 7d 6a 10 1 00 0 1 1 (h) (h) (h) (h) 06.69 06,6a 7d,6a window area 06,10 7d,10 7d 06 6a 10 1 00 1 1 1 (h) (h) (h) (h) 7d,69 06,6a 7d,6a NJU6854 - 26 - ver.2004-06-29 (3-4) segment shift direction the ddram access direction can be selected through setting the d 7 (ref) bit of the display control register (display), this function enables to reverse segment shift direction to reduce the restriction on the ic location on an lcd module. (3-5) block diagram of ddram and peripheral circuit grayscale control circuit segment data ref,swap y address (00 h ~83 h ) y register y counter line counter hst registe r data latch internal data bus display data ram x address counter x register ref x -address (00 h -83 h ) y address data write read data mpu i/ f segment output i/f NJU6854 -27- ver.2004-06-29 (3-6) ddram mapping (3-6-1) (rew, swap) = (0,0), shift1 = ?0?, shift0 = ?0?, vpc = "84h? (1/132 duty), fvc = "00h", hct = ?00h?, ssc1 and ssc2 = ?0?, en3ptl = ?0? hst=00 h hst=05 h com output ram address ---------- y address d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 ---------- d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 coma0 00 h coma1 01 h coma2 02 h 03 h 04 h 05 h 06 h 07 h coma63 3fh coma64 40 h coma65 41 h comb0 42 h comb1 43 h comb2 44 h comb3 45 h 46 h 47 h 48 h 49 h comb63 81 h comb64 82 h comb65 83 h se g ment out p u t ---------- sega 0 segb 0 segc0 sega131 segb131 segc131 --------------------------------------- --------------------------------------- --------------------------------------- --------------------------------------- --------------------------------------- --------------------------------------- --------------------------------------- --------------------------------------- x address x=00 h x=83 h ---------- NJU6854 - 28 - ver.2004-06-29 (3-6-2) (rew, swap) = (0,0), shift1 = ?0?, shift0 = ?0?, vpc = "70h? (1/112 duty), fvc = "00h", hct = ?0ah?, ssc1 and ssc2 = ?0?, en3ptl = ?0? hst=00h hst=05h com output ram addres s --------- - y address d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 ---------- d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 coma0 00h coma1 01h coma2 02h coma3 03h coma4 04h coma 5 05h coma6 06h coma7 07h coma8 coma9 coma1 0 coma11 coma1 2 35h 36h 37h 38h 39h 3a h 3b h 3c h 3d h 3e h coma6 3 3fh coma6 4 coma6 5 comb0 comb1 comb2 comb3 comb4 comb 5 comb6 comb7 comb8 comb9 comb1 0 comb11 comb1 2 6d h 6e h 6fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7a h 7b h 7c h 7d h 7e h 7fh 80h comb6 3 81h comb6 4 82h comb6 5 83h se g ment outpu t --------- - unused com driver unused com driver sega 0 segb 0 segc0 sega131 segb131 segc131 --------------------------------------- --------------------------------------- --------------------------------------- --------------------------------------- ------------------------ - ------------------------ - ------------------------ - --------------------------------------- x address x=00h x=83 h ---------- NJU6854 -29- ver.2004-06-29 (3-7) the relationship among bit assignment, x address and segment driver three sub pixels(r, g, b) individually driven by 3 segment drivers (segai, segbi, segci) consist one pixel of the color stn panel. in the 65k display mode, 5-bit display data for segai and segci can output 32-level grayscale respectively, and 6-bit display data for segbi can output 64-level grayscale, so the total quantity of possible colors is 65,536(32x32x64). in 4k-color mode, 4-bit display data for every segai, segbi and segci, so the total quantity of possible colors is 4,096(16x16x16). weighting value of display data is dependent on the status of the swap bit and the ref bit of display register. 16-bit bus access (65k-color mode) palette cj palette bj palette aj pwm control pwm control segci segbi segai msb lsb x address : nh note internal access x address : nh (ref = 0) :83h - nh (ref = 1) i = 0 to 131 grayscale palette j = 0 to 31 grayscale control pwmm[1:0]=00 for 64 level pwmm[1:0]=01 for 32 level pwmm[1:0]=11 for 128 level mpu write data mode[1:0] = 00 (ref,swap)=(0,0) or (1,1) moded = 0 (65,536 color display) pwm control + 2 frc display data d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 palette cj palette bj palette aj pwm control pwm control segci segbi segai msb lsb x address : nh note internal access x address : nh (ref = 0) :83h - nh (ref = 1) i = 0 to 131 grayscale palette j = 0 to 31 grayscale control pwmm[1:0]=00 for 64 level pwmm[1:0]=01 for 32 level pwmm[1:0]=11 for 128 level mpu write data mode[1:0] = 00 (ref,swap)=(0,0) or (1,1) moded = 0 (65,536 color display) pwm control + 2 frc display data d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 palette aj palette bj palette cj pwm control pwm control segci segbi segai msb lsb x address : nh note internal access x address : nh (ref= 0) :83h - nh (ref= 1) i = 0 to 131 grayscale palette j = 0 to 31 grayscale control pwmm[1:0]=00 for 64 level pwmm[1:0]=01 for 32 level pwmm[1:0]=11 for 128 level mode[1:0] = 00 (ref,swap)=(0,1) or (1,0) moded = 0 (65,536 color display) pwm control + 2 frc mpu write data display data d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10d9d8d7d6d5 palette aj palette bj palette cj pwm control pwm control segci segbi segai msb lsb x address : nh note internal access x address : nh (ref= 0) :83h - nh (ref= 1) i = 0 to 131 grayscale palette j = 0 to 31 grayscale control pwmm[1:0]=00 for 64 level pwmm[1:0]=01 for 32 level pwmm[1:0]=11 for 128 level mode[1:0] = 00 (ref,swap)=(0,1) or (1,0) moded = 0 (65,536 color display) pwm control + 2 frc mpu write data display data d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10d9d8d7d6d5 NJU6854 - 30 - ver.2004-06-29 16-bit bus access (4k-color mode 1) palette cj palette bj palette aj segci segbi segai msb lsb x address : nh note internal access x address : nh (ref = 0) :83h - nh (ref = 1) i = 0 to 131 grayscale palette j = 1, 3, 5 ... 29, 31 grayscale control pwmm[1:0]=00 for 64 level pwmm[1:0]=01 for 32 level pwmm[1:0]=10 for 16 level pwmm[1:0]=11 for 128 level mpu write data mode[1:0] = 01 (ref,swap)=(0,0) or (1,1) moded = 1 (4,096 color display) pwm control pwm control pwm control display data d15 d14 d13 d12 d10 d9 d8 d7 d4 d3 d2 d1 d15 d14 d13 d12 d10 d9 d8 d7 d4 d3 d2 d1 palette cj palette bj palette aj segci segbi segai msb lsb x address : nh note internal access x address : nh (ref = 0) :83h - nh (ref = 1) i = 0 to 131 grayscale palette j = 1, 3, 5 ... 29, 31 grayscale control pwmm[1:0]=00 for 64 level pwmm[1:0]=01 for 32 level pwmm[1:0]=10 for 16 level pwmm[1:0]=11 for 128 level mpu write data mode[1:0] = 01 (ref,swap)=(0,0) or (1,1) moded = 1 (4,096 color display) pwm control pwm control pwm control display data d15 d14 d13 d12 d10 d9 d8 d7 d4 d3 d2 d1 d15 d14 d13 d12 d10 d9 d8 d7 d4 d3 d2 d1 palette aj palette bj palette cj segci segbi segai msb lsb x address : nh note internal access x address : nh (ref = 0) :83h - nh (ref = 1) i = 0 to 131 grayscale control pwmm[1:0]=00 for 64 level pwmm[1:0]=01 for 32 level pwmm[1:0]=10 for 16 level pwmm[1:0]=11 for 128 level mpu write data mode[1:0] = 01 (ref,swap)=(0,1) or (1,0) moded = 1 (4,096 color display) pwm control pwm control pwm control display data grayscale palette j = 1, 3, 5 ... 29, 31 d15 d14 d13 d12 d10 d9 d8 d7 d4 d3 d2 d1 d15 d14 d13 d12 d10d9d8d7 d4 d3 d2 d1 palette aj palette bj palette cj segci segbi segai msb lsb x address : nh note internal access x address : nh (ref = 0) :83h - nh (ref = 1) i = 0 to 131 grayscale control pwmm[1:0]=00 for 64 level pwmm[1:0]=01 for 32 level pwmm[1:0]=10 for 16 level pwmm[1:0]=11 for 128 level mpu write data mode[1:0] = 01 (ref,swap)=(0,1) or (1,0) moded = 1 (4,096 color display) pwm control pwm control pwm control display data grayscale palette j = 1, 3, 5 ... 29, 31 d15 d14 d13 d12 d10 d9 d8 d7 d4 d3 d2 d1 d15 d14 d13 d12 d10d9d8d7 d4 d3 d2 d1 NJU6854 -31- ver.2004-06-29 16-bit bus access (4k-color mode 2) palette cj palette bj palette aj segci segbi segai msb lsb x address : nh note internal access x address : nh (ref = 0) :83h - nh (ref = 1) i = 0 to 131 grayscale palette j = 1, 3, 5 ... 29, 31 grayscale control pwmm[1:0]=00 for 64 level pwmm[1:0]=01 for 32 level pwmm[1:0]=10 for 16 level pwmm[1:0]=11 for 128 level mpu write data mode[1:0] = 10 (upper 4 bit invalid) (ref,swap)=(0,0) or (1,1) moded = 1 (4,096 color display) pwm control pwm control pwm control display data d11 d6 d5 d0 d10d9d8d7 d4d3d2d1 d0 d3 d2 d1 d6 d5 d7 d4 d11 d10 d9 d8 palette cj palette bj palette aj segci segbi segai msb lsb x address : nh note internal access x address : nh (ref = 0) :83h - nh (ref = 1) i = 0 to 131 grayscale palette j = 1, 3, 5 ... 29, 31 grayscale control pwmm[1:0]=00 for 64 level pwmm[1:0]=01 for 32 level pwmm[1:0]=10 for 16 level pwmm[1:0]=11 for 128 level mpu write data mode[1:0] = 10 (upper 4 bit invalid) (ref,swap)=(0,0) or (1,1) moded = 1 (4,096 color display) pwm control pwm control pwm control display data d11 d6 d5 d0 d10d9d8d7 d4d3d2d1 d0 d3 d2 d1 d6 d5 d7 d4 d11 d10 d9 d8 palette aj palette bj palette cj segci segbi segai msb lsb x address : nh note internal access x address : nh (ref = 0) :83h - nh (ref = 1) i = 0 to 131 grayscale control pwmm[1:0]=00 for 64 level pwmm[1:0]=01 for 32 level pwmm[1:0]=10 for 16 level pwmm[1:0]=11 for 128 level mpu write data mode[1:0] = 10 upper 4 bit invalid (ref,swap)=(0,1) or (1,0) moded = 1 (4,096 color display) pwm control pwm control pwm control display data grayscale palette j = 1, 3, 5 ... 29, 31 d11 d6 d5 d0 d10d9d8d7 d4d3d2d1 d11 d10 d9 d8 d0 d3 d2 d1 d6 d5 d7 d4 palette aj palette bj palette cj segci segbi segai msb lsb x address : nh note internal access x address : nh (ref = 0) :83h - nh (ref = 1) i = 0 to 131 grayscale control pwmm[1:0]=00 for 64 level pwmm[1:0]=01 for 32 level pwmm[1:0]=10 for 16 level pwmm[1:0]=11 for 128 level mpu write data mode[1:0] = 10 upper 4 bit invalid (ref,swap)=(0,1) or (1,0) moded = 1 (4,096 color display) pwm control pwm control pwm control display data grayscale palette j = 1, 3, 5 ... 29, 31 d11 d6 d5 d0 d10d9d8d7 d4d3d2d1 d11 d10 d9 d8 d0 d3 d2 d1 d6 d5 d7 d4 NJU6854 - 32 - ver.2004-06-29 relationship among display data, x address and segment drivers(16-bit access mode) 65k-color mode, mode[1:0]=0 h idsx ref swap 0 1 x address / display data / grayscale palette / segment driver 0 0 00 h 83 h 00 h 83 h x = 00 h : x = 83 h 1 1 83 h 00 h 83 h 00 h x = 83 h : x = 00 h 0 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 : d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 uds 1 d8 d9 d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 : d8 d9 d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 palette a palette b palette c : palette a palette b palette c sega0 segb0 segc0 : sega131 segb131 segc131 idsx ref swap 0 1 x address / display data / grayscale palette / segment driver 0 1 00 h 83 h 00 h 83 h x = 00 h : x = 83 h 1 0 83 h 00 h 83 h 00 h x = 83 h : x = 00 h 0 d11 d12 d13 d14 d15 d5 d6 d7 d8 d9 d10 d0 d1 d2 d3 d4 : d11 d12 d13 d14 d15 d5 d6 d7 d8 d9 d10 d0 d1 d2 d3 d4 uds 1 d3 d4 d5 d6 d7 d13 d14 d15 d0 d1 d2 d8 d9 d10 d11 d12 : d3 d4 d5 d6 d7 d13 d14 d15 d0 d1 d2 d8 d9 d10 d11 d12 palette c palette b palette a : palette c palette b palette a sega0 segb0 segc0 : sega131 segb131 segc131 4k-color mode 1, mode[1:0]=1 h idsx ref swap 0 1 x address / display data / grayscale palette / segment driver 0 0 00 h 83 h 00 h 83 h x = 00 h : x = 83 h 1 1 83 h 00 h 83 h 00 h x = 83 h : x = 00 h 0 d1 d2 d3 d4 d7 d8 d9 d10 d12 d13 d14 d15 : d1 d2 d3 d4 d7 d8 d9 d10 d12 d13 d14 d15 uds 1 d9 d10 d11 d12 d15 d0 d1 d2 d4 d5 d6 d7 : d9 d10 d11 d12 d15 d0 d1 d2 d4 d5 d6 d7 palette a palette b palette c : palette a palette b palette c sega0 segb0 segc0 : sega131 segb131 segc131 idsx ref swap 0 1 x address / display data / grayscale palette / segment driver 0 1 00 h 83 h 00 h 83 h x = 00 h : x = 83 h 1 0 83 h 00 h 83 h 00 h x = 83 h : x = 00 h 0 d12 d13 d14 d15 d7 d8 d9 d10 d1 d2 d3 d4 : d12 d13 d14 d15 d7 d8 d9 d10 d1 d2 d3 d4 uds 1 d4 d5 d6 d7 d15 d0 d1 d2 d9 d10 d11 d12 : d4 d5 d6 d7 d15 d0 d1 d2 d9 d10 d11 d12 palette c palette b palette a : palette c palette b palette a sega0 segb0 segc0 : sega131 segb131 segc131 NJU6854 -33- ver.2004-06-29 4k-color mode, mode[1:0]=2 h idsx ref swap 0 1 x address / display data / grayscale palette / segment driver 0 0 00 h 83 h 00 h 83 h x = 00 h : x = 83 h 1 1 83 h 00 h 83 h 00 h x = 83 h : x = 00 h 0 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 : d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 uds 1 d8 d9 d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 : d8 d9 d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 palette a palette b palette c : palette a palette b palette c sega0 segb0 segc0 : sega131 segb131 segc131 idsx ref swap 0 1 x address / display data / grayscale palette / segment driver 0 1 00 h 83 h 00 h 83 h x = 00 h : x = 83 h 1 0 83 h 00 h 83 h 00 h x = 83 h : x = 00 h 0 d8 d9 d10 d11 d4 d5 d6 d7 d0 d1 d2 d3 : d8 d9 d10 d11 d4 d5 d6 d7 d0 d1 d2 d3 uds 1 d0 d1 d2 d3 d12 d13 d14 d15 d8 d9 d10 d11 : d0 d1 d2 d3 d12 d13 d14 d15 d8 d9 d10 d11 palette c palette b palette a : palette c palette b palette a sega0 segb0 segc0 : sega131 segb131 segc131 NJU6854 - 34 - ver.2004-06-29 relationship among display data, x address and segment drivers(8-bit access mode) 1 st write in data d01 d11 d21 d31 d41 d51 d61 d71 2 nd write in data d02 d12 d22 d32 d42 d52 d62 d72 65k-color mode, mode[1:0]=0 h idsx ref swap 0 1 x address / display data / grayscale palette / segment driver 0 0 00 h 83 h 00 h 83 h x = 00 h : x = 83 h 1 1 83 h 00 h 83 h 00 h x = 83 h : x = 00 h 0 d01 d11 d21 d31 d41 d51 d61 d71 d02 d12 d22 d32 d42 d52 d62 d72 : d01 d11 d21 d31 d41 d51 d61 d71 d02 d12 d22 d32 d42 d52 d62 d72 uds 1 d02 d12 d22 d32 d42 d52 d62 d72 d01 d11 d21 d31 d41 d51 d61 d71 : d02 d12 d22 d32 d42 d52 d62 d72 d01 d11 d21 d31 d41 d51 d61 d71 palette a palette b palette c : palette a palette b palette c sega0 segb0 segc0 : sega131 segb131 segc131 idsx ref swap 0 1 x address / display data / grayscale palette / segment driver 0 1 00 h 83 h 00 h 83 h x = 00 h : x = 83 h 1 0 83 h 00 h 83 h 00 h x = 83 h : x = 00 h 0 d32 d42 d52 d62 d72 d51 d61 d71 d02 d12 d22 d01 d11 d21 d31 d41 : d32 d42 d52 d62 d72 d51 d61 d71 d02 d12 d22 d01 d11 d21 d31 d41 uds 1 d31 d41 d51 d61 d71 d52 d62 d72 d01 d11 d21 d02 d12 d22 d32 d42 : d31 d41 d51 d61 d71 d52 d62 d72 d01 d11 d21 d02 d12 d22 d32 d42 palette c palette b palette a : palette c palette b palette a sega0 segb0 segc0 : sega131 segb131 segc131 4k-color mode, mode[1:0]=1 h idsx ref swap 0 1 x address / display data / grayscale palette / segment driver 0 0 00 h 83 h 00 h 83 h x = 00 h : x = 83 h 1 1 83 h 00 h 83 h 00 h x = 83 h : x = 00 h 0 d11 d21 d31 d41 d71 d02 d12 d22 d42 d52 d62 d72 : d11 d21 d31 d41 d71 d02 d12 d22 d42 d52 d62 d72 uds 1 d12 d22 d32 d42 d72 d01 d11 d21 d41 d51 d61 d71 : d12 d22 d32 d42 d72 d01 d11 d21 d41 d51 d61 d71 palette a palette b palette c : palette a palette b palette c sega0 segb0 segc0 : sega131 segb131 segc131 idsx ref swap 0 1 x address / display data / grayscale palette / segment driver 0 1 00 h 83 h 00 h 83 h x = 00 h : x = 83 h 1 0 83 h 00 h 83 h 00 h x = 83 h : x = 00 h 0 d42 d52 d62 d72 d71 d02 d12 d22 d11 d21 d31 d41 : d42 d52 d62 d72 d71 d02 d12 d22 d11 d21 d31 d41 uds 1 d41 d51 d61 d71 d72 d01 d11 d21 d12 d22 d32 d42 : d41 d51 d61 d71 d72 d01 d11 d21 d12 d22 d32 d42 palette c palette b palette a : palette c palette b palette a sega0 segb0 segc0 : sega131 segb131 segc131 NJU6854 -35- ver.2004-06-29 4k-color mode, mode[1:0]=2 h idsx ref swap 0 1 x address / display data / grayscale palette / segment driver 0 0 00 h 83 h 00 h 83 h x = 00 h : x = 83 h 1 1 83 h 00 h 83 h 00 h x = 83 h : x = 00 h 0 d01 d11 d21 d31 d41 d51 d61 d71 d02 d12 d22 d32 : d01 d11 d21 d31 d41 d51 d61 d71 d02 d12 d22 d32 uds 1 d02 d12 d22 d32 d42 d52 d62 d72 d01 d11 d21 d31 : d02 d12 d22 d32 d42 d52 d62 d72 d01 d11 d21 d31 palette a palette b palette c : palette a palette b palette c sega0 segb0 segc0 : sega131 segb131 segc131 idsx ref swap 0 1 x address / display data / grayscale palette / segment driver 0 1 00 h 83 h 00 h 83 h x = 00 h : x = 83 h 1 0 83 h 00 h 83 h 00 h x = 83 h : x = 00 h 0 d02 d12 d22 d32 d41 d51 d61 d71 d01 d11 d21 d31 : d02 d12 d22 d32 d41 d51 d61 d71 d01 d11 d21 d31 uds 1 d01 d11 d21 d31 d42 d52 d62 d72 d02 d12 d22 d32 : d01 d11 d21 d31 d42 d52 d62 d72 d02 d12 d22 d32 palette c palette b palette a : palette c palette b palette a sega0 segb0 segc0 : sega131 segb131 segc131 NJU6854 - 36 - ver.2004-06-29 (4) pwm control there are three variable grayscale modes and one fixed grayscale mode for NJU6854. in the 65k variable grayscale mode ((pwmm1,pwmm0)=(1,1)), every aj, bj and cj(j=0-31) grayscale palette can select one of 32 pwm values from 128 levels(0/127~127/127). in the 4k mode, every aj, bj and cj(j=0-31) grayscale palette can select one of 16 pwm values from 128 levels (0/127~127/127). table 8 pwm and grayscale mode pwmm1 pwmm0 grayscale mode grayscale display mode 0 0 variable 32 options from 64 levels 65k-color mode , or 16 options 4k-color mode 0 1 variable 32 options from 32 levels 65k-color mode , or 16 options 4k-color mode 1 0 fixed 16 options from 16 levels 4k-color mode 1 1 variable 32 options from 128 levels 65k-color mode , or 16 options 4k-color mode (5) frame rate control(frc) frc (frame rate control) is the method which averages pwm value (grayscale level) by changing this value by the frame. the frc is used for the segbi (palette bj) in combination with pwm control in the 65k mode, so that the segbi can generate 64 grayscales (32 grayscales x 2) by total 6 bits data (5-bit pwm data and 1-bit frc data). (6) display timing generator the display timing generator generates timing clocks such as the lp (latch pulse), m (frame rate) and flm (first line maker) by dividing an oscillation frequency. the lp is used for the line counter and the data latch circuit. at the rising edge of the lp signal, the line counter is counted up, then display data is latched into the data latch circuit. at the falling edge of the lp signal, the latch data is released to the grayscale control circuit, then segment drivers ai, bi and ci (i=0~131) produce lcd driving waveforms. the internal data-transmission timing between the ddram and segment drivers is completely independent of external data-transmission timing, so that mpu makes access to the lsi without concern for the lsi?s internal operation. the m toggles once every frame in the default status, and can be programmed to toggle once every n lines. and the flm is used to specify an initial display line, which is preset whenever the flm becomes ?h?. (7) data latch circuit the data latch circuit is used to temporarily store display data which is released to the grayscale control circuit. the display data in this circuit is updated in synchronization with the lp. the ?display on/off? and ?reverse display on/off? instructions control the data in this circuit, but does not change the data in the ddram. NJU6854 -37- ver.2004-06-29 (8) common drivers and segment drivers the lsi includes 132-common drivers and 396-segment drivers. the common drivers generate lcd driving waveforms formed on the v 0 , v 1 , v 4 and v ssh levels. the segment drivers generate waveforms formed on the v 0 , v 2 , v 3 and v ssh levels. fig 6 lcd driving waveforms (1/132duty) lp flm m coma0 coma1 coma2 sega segb segc segc segb sega segc segb sega segc segb sega coma0 coma1 coma2 coma0 coma1 coma2 coma0 coma1 coma2 lp flm m coma0 coma1 coma2 sega segb segc segc segb sega segc segb sega segc segb sega coma0 coma1 coma2 coma0 coma1 coma2 coma0 coma1 coma2 NJU6854 - 38 - ver.2004-06-29 (9) oscillator the oscillator consists of a resistor and a capacitor, and generates internal clocks for the display timing generator and the voltage booster. through oscillation control register(cr), oscillating signal can be generated by using the internal resistor or an external resistor. besides, external clock can be used too. if using the internal resistor, ground osci pin and keep osco pin open. frequency can be adjusted or divided by using frequency control register(mdiv). if using the external resistor, connect osci and osco with an resistor. if using external clock, input 50% duty signal to the osci pin. (10) lcd power supply the internal lcd power supply is organized into the voltage converter and the voltage booster. the voltage converter consists of the reference voltage generator with temperature compensation circuit, the voltage regulator with evr control and the lcd bias voltage generator. furthermore the configuration of the lcd power supply can be arranged by setting power control 1 register(tcbi) and power control 2 register (pow2). it is possible to use part of the internal lcd power supply with an external supply, as shown in table 17. table 9 configuration of lcd power supply voltage converter dcon ampon vgoff vbon voltage booster voltage regulator (v reg output) reference voltage generator (v ba output) lcd bias generator external power supply note 0 0 x x disable disable disable disable v out , v 0 , v 1 , v 2 , v 3 and v 4 are supplied 1 0 0 enable disable v out , v ref are supplied 2 1 x disable disable v out , v reg are supplied 3 0 1 0 1 disable enable enable enable v out is supplied 4 0 0 enable disable v ref is supplied 5 1 x disable disable v reg is supplied 6 1 1 0 1 enalble enable enable enable note1) the lcd bias voltages are externally supplied, and c1, c2, c3, c4, c5, v ref , v reg and v ee are open. note2) the v out and v ref are externally supplied, and the c1, c2, c3, c4, c5 and v ee are open. note3) the v out and v reg are externally supplied, and the c1, c2, c3, c4, c5 and v ee are open. note4) the v out is externally supplied, and the c1, c2, c3, c4 and c5 are open. note5) the v ref is externally supplied. note6) the v reg is externally supplied NJU6854 -39- ver.2004-06-29 (10-1) voltage booster the internal voltage booster generates up to 6 x v ee voltage. the boost level is selected from 2 x ~6 x by setting the boost level register(gvu). the boost voltage v out must not exceed 18.0v, otherwise the voltage stress may cause a permanent damage to the lsi. fig 7 boost voltage fig 8 external capacitor connection of voltage booster (10-2) electrical volume register (evr) the evr is used to fine-tune the v 0 voltage to optimize display contrast. the evr value is controlled in 128 steps by setting the electrical volume register(evol). 6-time boost 3-time boost 2-time boost 4-time boost 5-time boost c 1+ c 1 - c 2+ c 2 - c 3+ c 3 - c 4+ c 4 - c 5+ c 5 - v out v ssh + + + + + + c 1+ c 1 - c 2+ c 2 - c 3+ c 3 - c 4+ c 4 - c 5+ c 5 - v out v ssh + + + + + + + + + + + + c 1+ c 1 - c 2+ c 2 - c 3+ c 3 - c 4+ c 4 - c 5+ c 5 - v out v ssh + + + + + c 1+ c 1 - c 2+ c 2 - c 3+ c 3 - c 4+ c 4 - c 5+ c 5 - v out v ssh + + + + + + + + + + c 1+ c 1 - c 2+ c 2 - c 3+ c 3 - c 4+ c 4 - c 5+ c 5 - v out v ssh + + + + c 1+ c 1 - c 2+ c 2 - c 3+ c 3 - c 4+ c 4 - c 5+ c 5 - v out v ssh + + + + + + + + c 1+ c 1 - c 2+ c 2 - c 3+ c 3 - c 4+ c 4 - c 5+ c 5 - v out v ssh + + + c 1+ c 1 - c 2+ c 2 - c 3+ c 3 - c 4+ c 4 - c 5+ c 5 - v out v ssh + + + + + + c 1+ c 1 - c 2+ c 2 - c 3+ c 3 - c 4+ c 4 - c 5+ c 5 - v out v ssh + + c 1+ c 1 - c 2+ c 2 - c 3+ c 3 - c 4+ c 4 - c 5+ c 5 - v out v ssh + + + + 3-time boost 6-time boost v ssh =0v v ee =3v v out =9v v out =18.0v v ssh =0v v ee =3v 3-time boost 6-time boost v ssh =0v v ee =3v v out =9v v out =18.0v v ssh =0v v ee =3v NJU6854 - 40 - ver.2004-06-29 (10-3) voltage converter (10-3-1) voltage regulator the voltage regulator consists of an operational amplifier with gain control and evr. the v ref voltage is multiplied to obtain the v reg voltage, and gain control is set by the gsel bit of the boost level register (gvu). when gsel=0, boost level is determined by vu 2 ~vu 0 bits value. when gsel=1, booster level is determined by rg 2 ~rg 0 bit value. the relationship of v reg and lcd driving voltage(v 0 ) is shown as below: fig 9 relationship of v 0 and v reg table 10 v reg gain gsel = ?0? gsel = ?1? vu2 vu1 vu0 rg2 rg1 rg0 v reg gain remark 0 0 0 - default vu[2:0] 0 0 1 2 0 1 0 0 0 0 3 default rg[2:0] 0 1 1 0 0 1 4 1 0 0 0 1 0 5 1 0 1 0 1 1 6 1 0 0 6.45 1 0 1 7 1 1 0 7.3 1 1 1 8.0 1 1 0 - 1 1 1 - v reg can be calculated by the following equation: v reg = v ref x n (n: boost level) note) to stabilize the v reg , connect a capacitor to the v reg pin. available v 0 voltage range by control v reg gain evr =00 h evr =7f h 18 16 14 12 10 8 6 4 2 v reg gain volt evr =00 h evr =7f h v ref =2.7v external reference v ref =1.9v internal reference 2 x 3 x 4 x 5 x 6 x 6.45 x 7 x 7.3 x 8.0 x available v 0 voltage range by control v reg gain evr =00 h evr =7f h 18 16 14 12 10 8 6 4 2 v reg gain volt evr =00 h evr =7f h v ref =2.7v external reference v ref =1.9v internal reference 2 x 3 x 4 x 5 x 6 x 6.45 x 7 x 7.3 x 8.0 x NJU6854 -41- ver.2004-06-29 (10-3-2) reference voltage generator the reference voltage generator outputs about 1.9v reference voltage. when using the internal lcd power supply, connect the v ba and the v ref . when using an external lcd power supply, input external power into v ref pin and keep v ba open. the temperature compensating circuit is built in, compensation coefficient can be selected from the following shown 4 levels by setting tcv1~tvc0 bits of power control 1 register(tcbi). fig 10 temperature compensation table 11 temperature coefficient selection tcv[1] tcv[0] v ba output remark 0 0 0.0 % / c default setting 0 1 - 0.13 % / c 1 0 - 0.20 % / c 1 1 - 0.24 % / c (10-3-3) lcd bias voltage generator the lcd bias voltage generator consists of buffer amplifiers and bleeder resistors, and the bias ratio can be selected from1/5~1/12 through setting b2~b0 bits of power control 1 register(tcbi). 30 reference voltage temperature -0.0% / c -0.13% / c -0.20% / c -0.24% /c -30 0 60 -0.0% / c 1.9 30 reference voltage temperature -0.0% / c -0.13% / c -0.20% / c -0.24% /c -30 0 60 -0.0% / c 1.9 NJU6854 - 42 - ver.2004-06-29 (10-4) external components for lcd power supply fig 11 fig 12 reference guide values of capacitor ca 1 0.47 ~ 4.7 uf ca 2 0.47 ~ 2.2 uf ca 3 0~0.1uf note1) b grade capacitor is recommended for ca1-ca3. make sure what is the best capacitor value in the particular application. note2) parasitic resistance on the power supply lines (v dd , v ss , v ee , v ssh , v out , v 0 , v 1 , v 2 , v 3 and v 4 ) reduces step-up efficiency of the voltage booster, and may have an impact on the lsi?s operation and display quality. to minimize this impact, be sure to lay out the shortest wires and place capacitors as close to the lsi as possible. using external power supply only using internal power supply v dd v ee v ba v ref v reg c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - v out v 0 v 1 v 2 v 3 v 4 NJU6854 v ss v ss ca 1 ca 2 ca 2 ca 2 ca 2 ca 2 ca 1 ca 1 ca 1 ca 1 ca 1 v ss ca 3 v ss ca 3 v dd v ee v ba v ref v reg c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - v out v 0 v 1 v 2 v 3 v 4 NJU6854 v ss v ss ca 1 ca 2 ca 2 ca 2 ca 2 ca 2 ca 1 ca 1 ca 1 ca 1 ca 1 v ss ca 3 v ss ca 3 v dd v ee v ba v ref v reg c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - v out v 0 v 1 v 2 v 3 v 4 NJU6854 external power circuit v 0 v 1 v 2 v 3 v 4 v dd v ee v ba v ref v reg c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - v out v 0 v 1 v 2 v 3 v 4 NJU6854 external power circuit v 0 v 1 v 2 v 3 v 4 NJU6854 -43- ver.2004-06-29 fig 11 fig 12 reference guide values of capacitor ca 1 0.47 ~ 4.7 uf ca 2 0.47 ~ 2.2 uf ca 3 0~0.1uf note1) b grade capacitor is recommended for ca1-ca3. make sure what is the best capacitor value in the particular application. note2) parasitic resistance on the power supply lines (v dd , v ss , v ee , v ssh , v out , v 0 , v 1 , v 2 , v 3 and v 4 ) reduces step-up efficiency of the voltage booster, and may have an impact on the lsi?s operation and display quality. to minimize this impact, be sure to lay out the shortest wires and place capacitors as close to the lsi as possible. . using internal power supply without reference voltage generator(1) using internal power supply without reference voltage generator(2) v dd v ee v ba v ref v reg c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - v out v 0 v 1 v 2 v 3 v 4 NJU6854 v ss v ss ca 1 ca 2 ca 2 ca 2 ca 2 ca 2 ca 1 ca 1 ca 1 ca 1 ca 1 v ss ca 3 ca 3 v dd v ee v ba v ref v reg c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - v out v 0 v 1 v 2 v 3 v 4 NJU6854 v ss v ss ca 1 ca 2 ca 2 ca 2 ca 2 ca 2 ca 1 ca 1 ca 1 ca 1 ca 1 v ss ca 3 ca 3 v dd v ee v ba v ref v reg c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - v out v 0 v 1 v 2 v 3 v 4 NJU6854 v ss v ss ca 1 ca 2 ca 2 ca 2 ca 2 ca 2 ca 1 ca 1 ca 1 ca 1 ca 1 v ss ca 3 ca 3 thermistor v dd v ee v ba v ref v reg c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - v out v 0 v 1 v 2 v 3 v 4 NJU6854 v ss v ss ca 1 ca 2 ca 2 ca 2 ca 2 ca 2 ca 1 ca 1 ca 1 ca 1 ca 1 v ss ca 3 ca 3 thermistor NJU6854 - 44 - ver.2004-06-29 fig 15 reference guide values of capacitor ca 1 0.47 ~ 4.7 uf ca 2 0.47 ~ 2.2 uf ca 3 0~0.1uf note1) b grade capacitor is recommended for ca1-ca3. make sure what is the best capacitor value in the particular application. note2) parasitic resistance on the power supply lines (v dd , v ss , v ee , v ssh , v out , v 0 , v 1 , v 2 , v 3 and v 4 ) reduces step-up efficiency of the voltage booster, and may have an impact on the lsi?s operation and display quality. to minimize this impact, be sure to lay out the shortest wires and place capacitors as close to the lsi as possible. using internal power supply without voltage booster v dd v ee v ba v ref v reg c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - v out v 0 v 1 v 2 v 3 v 4 NJU6854 v ss ca 2 ca 2 ca 2 ca 2 ca 2 v ss ca 3 external power circuit v dd v ee v ba v ref v reg c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - v out v 0 v 1 v 2 v 3 v 4 NJU6854 v ss ca 2 ca 2 ca 2 ca 2 ca 2 v ss ca 3 external power circuit NJU6854 -45- ver.2004-06-29 (10-5) power on/off to protect the lsi from over current, the following sequences must be maintained to turn on and off the power supply. using internal lcd power supply power on first ?v dd and v ee on?, next ?reset by resb?, then ?internal lcd power supply on?. be sure to execute the ?display on? instruction later than the completion of this power on sequence. otherwise, unexpected pixels may be turned on instantly. power off first ?reset by resb or ?halt? instruction?, next ?v dd and v ee off?. if using different power sources for the v dd and the v ee , the v ee must be turned off after the reset or the ?halt?. after that, the v dd can be turned off, waiting until the lcd bias voltages (v 0 ~v 4 ) drop below the threshold level of lcd pixels. using external lcd power supply power on first ?v dd and v ee on?, next ?reset by resb?, then ?external lcd power supply on?. when using only external v out , first ?v dd on?, next ?reset by resb?, then ?external v out on?, as well. power off first ?reset by resb or ?halt? instruction? to isolate external lcd bias voltages, next ?v dd off?. for more safety, placing a resistor in series on the v 0 line (or the v out line in using only the external v out ) is recommended. that resistance is usually between 50 ? and 100 ? . fig 16 rising time of the power supply item recommended rising time applicable power tr 30 ? ~ 100 ? v dd , v ee note : the rising time is the time from 10% v dd to 90%v ee (10-6) discharge circuit the lsi incorporates two independently discharge circuits for the capacitors connected to v out and v 1 -v 4 . when setting dsi1 bit of discharge on/off register (disc) to ?1?, or executing reset instruction, the capacitors on v 1 -v 4 are discharged, by the same way, setting dsi2 to ?1? or resetting, the capacitor on v out is discharged. be sure to turn off the internal or external lcd power supply during discharging, otherwise discharge circuit will function as a current load and increase operating current. v dd , v ee v dd , v ee NJU6854 - 46 - ver.2004-06-29 (10-7) reset function the reset function initializes the lsi to the following default status by setting the resb to ?l?. usually connect the resb to mpu?s reset pin, so that the lsi and mpu are initialized simultaneously. table 12 default status item initial value ddram undefined y address 00 h x address 00 h ddram access increment mode x/y address increment on bus length 8bit initial display line 0 h (1 st line) display on/off off reverse display on/off off(normal) display clock monitor off duty cycle ratio 1/132 vertical blanking area 0 n-line inversion on/off off common scan direction coma0 coma65 comb0 comb65 ref ref=0(normal) swap off(normal) electronic volume register(evr) (0, 0, 0, 0, 0, 0) internal lcd power supply off display mode variable grayscale mode(64 grayscales) bias ratio 1/9 bias colors select 65,536 colors grayscale palette aj[6:0] default value grayscale palette bj[6:0] default value grayscale palette cj[6:0] default value extra palette pcx[6:0] default value pwm output mode forward pwm discharge on/off off(0) NJU6854 -47- ver.2004-06-29 (11) instruction tables table 0 [2:0] = 000 b ra[3:0] name d7 d6 d5 d4 d3 d2 d1 d0 remark 0 0000 cr * * * * * crf crs1 crs0 osc control 1 0001 cfg aim1 aim0 vwr idsy idsx win uds swif display data configuration /window area on/off /increment control 2 0010 vpc vpc7 vpc6 vpc5 vpc4 vpc3 vpc2 vpc1 vpc0 display line number 3 0011 fvc * * * * fvc3 fvc2 fvc1 fvc0 blank line number 4 0100 adrh xa7 xa6 xa5 xa4 xa3 xa2 xa1 xa0 ddram x address 5 0101 adrl ya7 ya6 ya5 ya4 ya3 ya2 ya1 ya0 ddram y address 6 0110 eadrh xea7 xea6 xea5 xea4 xea3 xea2 xea1 xea0 window end x address 7 0111 eadrl yea7 yea6 yea5 yea4 yea3 yea2 yea1 yea0 window end y address 8 1000 color pwmm1 pwmm0 * mode1 mode0 * * moded display mode/grayscale mode 9 1001 mdiv * mdiv2 mdiv1 mdiv0 * crb2 crb1 crb0 osc frequency control 10 1010 hct * hct6 hct5 hct4 hct3 hct2 hct1 hct0 header com 11 1011 hst hst7 hst6 hst5 hst4 hst3 hst2 hst1 hst0 initial display line 12 1100 ssc1 ssc17 ssc16 ssc15 ssc14 ssc13 ssc12 ssc11 ssc10 scan start com 1 13 1101 ssc2 ssc27 ssc26 ssc25 ssc24 ssc23 ssc22 ssc21 ssc20 scan start com 2 14 1110 pcc1 pcc17 pcc16 pcc15 pcc14 pcc13 pcc12 pcc11 pcc10 partial display line number1 15 1111 pcc2 pcc27 pcc26 pcc25 pcc24 pcc23 pcc22 pcc21 pcc20 partial display line number 2 table1 [2:0] = 001 b ra[3:0] name d7 d6 d5 d4 d3 d2 d1 d0 remark 0 0000 mc mc7 mc6 mc5 mc4 mc3 mc2 mc1 mc0 n-line inversion 1 0001 tcbi vgoff vbon tcv1 tcv0 * b2 b1 b0 power control 1 2 0010 evol * evol6 evol5 evol4 evol3 evol2 evol1 evol0 electronic volume 3 0011 pbx mon * * gs pbx3 pbx2 pbx1 pbx0 display timing signal monitor/grayscale palette bx 4 0100 * * * * * * * * * n/a 5 0101 pow2 * * * ckcont ampon halt dcon res power control 2 6 0110 gvu gsel rg2 rg1 rg0 * vu2 vu1 vu0 amplifier gain/ booster level 7 0111 bck bcks bckg * * bck3 bck2 bck1 bck0 booster clock 8 1000 display ref swap * shift1 shift0 tbc ten on/off display control 9 1001 pwm * * pwmc1 pwmc0 pwmb1 pwmb0 pwma1 pwma0 pwm mode control 10 1010 econt tst0 en3ptl enled rev led13 led12 led11 led10 3 partial display / led control / rev 11 1011 disc * * * * * * dis2 dis1 discharge control 12 1100 edata led27 led26 led25 led24 led23 led22 led21 led20 led control signal 13 1101 ra rss ra6 ra5 ra4 ra3 ra2 ra1 ra0 setting instruction table 14 1110 ssc3 ssc37 ssc36 ssc35 ssc34 ssc33 ssc32 ssc31 ssc30 scan start com 3 15 1111 pcc3 pcc37 pcc36 pcc35 pcc34 pcc33 pcc32 pcc31 pcc30 partial display line number3 NJU6854 - 48 - ver.2004-06-29 table2 [2:0] = 010 b ra[3:0] name d7 d6 d5 d4 d3 d2 d1 d0 remark 0 0000 pa0 * pa06 pa05 pa04 pa03 pa02 pa01 pa00 grayscale palette a0 (0/31) 1 0001 pa1 * pa16 pa15 pa14 pa13 pa12 pa11 pa10 grayscale palette a1 (1/31) 2 0010 pa2 * pa26 pa25 pa24 pa23 pa22 pa21 pa20 grayscale palette a2 (2/31) 3 0011 pa3 * pa36 pa35 pa34 pa33 pa32 pa31 pa30 grayscale palette a3 (3/31) 4 0100 pa4 * pa46 pa45 pa44 pa43 pa42 pa41 pa40 grayscale palette a4 (4/31) 5 0101 pa5 * pa56 pa55 pa54 pa53 pa52 pa51 pa50 grayscale palette a5 (5/31) 6 0110 pa6 * pa66 pa65 pa64 pa63 pa62 pa61 pa60 grayscale palette a6 (6/31) 7 0111 pa7 * pa76 pa75 pa74 pa73 pa72 pa71 pa70 grayscale palette a7 (7/31) 8 1000 pa8 * pa86 pa85 pa84 pa83 pa82 pa81 pa80 grayscale palette a8 (8/31) 9 1001 pa9 * pa96 pa95 pa94 pa93 pa92 pa91 pa90 grayscale palette a9 (9/31) 10 1010 pa10 * pa106 pa105 pa104 pa103 pa102 pa101 pa100 grayscale palette a10 (10/31) 11 1011 pa11 * pa116 pa115 pa114 pa113 pa112 pa111 pa110 grayscale palette a11 (11/31) 12 1100 pa12 * pa126 pa125 pa124 pa123 pa122 pa121 pa120 grayscale palette a12 (12/31) 13 1101 pa13 * pa136 pa135 pa134 pa133 pa132 pa131 pa130 grayscale palette a13 (13/31) 14 1110 pa14 * pa146 pa145 pa144 pa143 pa142 pa141 pa140 grayscale palette a14 (14/31) 15 1111 pa15 * pa156 pa155 pa154 pa153 pa152 pa151 pa150 grayscale palette a15 (15/31) table3 [2:0] = 011 b ra[3:0] name d7 d6 d5 d4 d3 d2 d1 d0 remark 0 0000 pa16 * pa166 pa165 pa164 pa163 pa162 pa161 pa160 grayscale palette a16 (16/31) 1 0001 pa17 * pa176 pa175 pa174 pa173 pa172 pa171 pa170 grayscale palette a17 (17/31) 2 0010 pa18 * pa186 pa185 pa184 pa183 pa182 pa181 pa180 grayscale palette a18 (18/31) 3 0011 pa19 * pa196 pa195 pa194 pa193 pa192 pa191 pa190 grayscale palette a19 (19/31) 4 0100 pa20 * pa206 pa205 pa204 pa203 pa202 pa201 pa200 grayscale palette a20 (20/31) 5 0101 pa21 * pa216 pa215 pa214 pa213 pa212 pa211 pa210 grayscale palette a21 (21/31) 6 0110 pa22 * pa226 pa225 pa224 pa223 pa222 pa221 pa220 grayscale palette a22 (22/31) 7 0111 pa23 * pa236 pa235 pa234 pa233 pa232 pa231 pa230 grayscale palette a23 (23/31) 8 1000 pa24 * pa246 pa245 pa244 pa243 pa242 pa241 pa240 grayscale palette a24 (24/31) 9 1001 pa25 * pa256 pa255 pa254 pa253 pa252 pa251 pa250 grayscale palette a25 (25/31) 10 1010 pa26 * pa266 pa265 pa264 pa263 pa262 pa261 pa260 grayscale palette a26 (26/31) 11 1011 pa27 * pa276 pa275 pa274 pa273 pa272 pa271 pa270 grayscale palette a27 (27/31) 12 1100 pa28 * pa286 pa285 pa284 pa283 pa282 pa281 pa280 grayscale palette a28 (28/31) 13 1101 pa29 * pa296 pa295 pa294 pa293 pa292 pa291 pa290 grayscale palette a29 (29/31) 14 1110 pa30 * pa306 pa305 pa304 pa303 pa302 pa301 pa300 grayscale palette a30 (30/31) 15 1111 pa31 * pa316 pa315 pa314 pa313 pa312 pa311 pa310 grayscale palette a31 (31/31) NJU6854 -49- ver.2004-06-29 table4 [2:0] = 100 b ra[3:0] name d7 d6 d5 d4 d3 d2 d1 d0 remark 0 0000 pb0 * pb06 pb05 pb04 pb03 pb02 pb01 pb00 grayscale palette b0 (0/31) 1 0001 pb1 * pb16 pb15 pb14 pb13 pb12 pb11 pb10 grayscale palette b1 (1/31) 2 0010 pb2 * pb26 pb25 pb24 pb23 pb22 pb21 pb20 grayscale palette b2 (2/31) 3 0011 pb3 * pb36 pb35 pb34 pb33 pb32 pb31 pb30 grayscale palette b3 (3/31) 4 0100 pb4 * pb46 pb45 pb44 pb43 pb42 pb41 pb40 grayscale palette b4 (4/31) 5 0101 pb5 * pb56 pb55 pb54 pb53 pb52 pb51 pb50 grayscale palette b5 (5/31) 6 0110 pb6 * pb66 pb65 pb64 pb63 pb62 pb61 pb60 grayscale palette b6 (6/31) 7 0111 pb7 * pb76 pb75 pb74 pb73 pb72 pb71 pb70 grayscale palette b7 (7/31) 8 1000 pb8 * pb86 pb85 pb84 pb83 pb82 pb81 pb80 grayscale palette b8 (8/31) 9 1001 pb9 * pb96 pb95 pb94 pb93 pb92 pb91 pb90 grayscale palette b9 (9/31) 10 1010 pb10 * pb106 pb105 pb104 pb103 pb102 pb101 pb100 grayscale palette b10 (10/31) 11 1011 pb11 * pb116 pb115 pb114 pb113 pb112 pb111 pb110 grayscale palette b11 (11/31) 12 1100 pb12 * pb126 pb125 pb124 pb123 pb122 pb121 pb120 grayscale palette b12 (12/31) 13 1101 pb13 * pb136 pb135 pb134 pb133 pb132 pb131 pb130 grayscale palette b13 (13/31) 14 1110 pb14 * pb146 pb145 pb144 pb143 pb142 pb141 pb140 grayscale palette b14 (14/31) 15 1111 pb15 * pb156 pb155 pb154 pb153 pb152 pb151 pb150 grayscale palette b15 (15/31) table5 [2:0] = 101 b ra[3:0] name d7 d6 d5 d4 d3 d2 d1 d0 remark 0 0000 pb16 * pb166 pb165 pb164 pb163 pb162 pb161 pb160 grayscale palette b16 (16/31) 1 0001 pb17 * pb176 pb175 pb174 pb173 pb172 pb171 pb170 grayscale palette b17 (17/31) 2 0010 pb18 * pb186 pb185 pb184 pb183 pb182 pb181 pb180 grayscale palette b18 (18/31) 3 0011 pb19 * pb196 pb195 pb194 pb193 pb192 pb191 pb190 grayscale palette b19 (19/31) 4 0100 pb20 * pb206 pb205 pb204 pb203 pb202 pb201 pb200 grayscale palette b20 (20/31) 5 0101 pb21 * pb216 pb215 pb214 pb213 pb212 pb211 pb210 grayscale palette b21 (21/31) 6 0110 pb22 * pb226 pb225 pb224 pb223 pb222 pb221 pb220 grayscale palette b22 (22/31) 7 0111 pb23 * pb236 pb235 pb234 pb233 pb232 pb231 pb230 grayscale palette b23 (23/31) 8 1000 pb24 * pb246 pb245 pb244 pb243 pb242 pb241 pb240 grayscale palette b24 (24/31) 9 1001 pb25 * pb256 pb255 pb254 pb253 pb252 pb251 pb250 grayscale palette b25 (25/31) 10 1010 pb26 * pb266 pb265 pb264 pb263 pb262 pb261 pb260 grayscale palette b26 (26/31) 11 1011 pb27 * pb276 pb275 pb274 pb273 pb272 pb271 pb270 grayscale palette b27 (27/31) 12 1100 pb28 * pb286 pb285 pb284 pb283 pb282 pb281 pb280 grayscale palette b28 (28/31) 13 1101 pb29 * pb296 pb295 pb294 pb293 pb292 pb291 pb290 grayscale palette b29 (29/31) 14 1110 pb30 * pb306 pb305 pb304 pb303 pb302 pb301 pb300 grayscale palette b30 (30/31) 15 1111 pb31 * pb316 pb315 pb314 pb313 pb312 pb311 pb310 grayscale palette b31 (31/31) NJU6854 - 50 - ver.2004-06-29 table6 [2:0] = 110 b ra[3:0] name d7 d6 d5 d4 d3 d2 d1 d0 remark 0 0000 pc0 * pc06 pc05 pc04 pc03 pc02 pc01 pc00 grayscale palette c0 (0/31) 1 0001 pc1 * pc16 pc15 pc14 pc13 pc12 pc11 pc10 grayscale palette c1 (1/31) 2 0010 pc2 * pc26 pc25 pc24 pc23 pc22 pc21 pc20 grayscale palette c2 (2/31) 3 0011 pc3 * pc36 pc35 pc34 pc33 pc32 pc31 pc30 grayscale palette c3 (3/31) 4 0100 pc4 * pc46 pc45 pc44 pc43 pc42 pc41 pc40 grayscale palette c4 (4/31) 5 0101 pc5 * pc56 pc55 pc54 pc53 pc52 pc51 pc50 grayscale palette c5 (5/31) 6 0110 pc6 * pc66 pc65 pc64 pc63 pc62 pc61 pc60 grayscale palette c6 (6/31) 7 0111 pc7 * pc76 pc75 pc74 pc73 pc72 pc71 pc70 grayscale palette c7 (7/31) 8 1000 pc8 * pc86 pc85 pc84 pc83 pc82 pc81 pc80 grayscale palette c8 (8/31) 9 1001 pc9 * pc96 pc95 pc94 pc93 pc92 pc91 pc90 grayscale palette c9 (9/31) 10 1010 pc10 * pc106 pc105 pc104 pc103 pc102 pc101 pc100 grayscale palette c10 (10/31) 11 1011 pc11 * pc116 pc115 pc114 pc113 pc112 pc111 pc110 grayscale palette c11 (11/31) 12 1100 pc12 * pc126 pc125 pc124 pc123 pc122 pc121 pc120 grayscale palette c12 (12/31) 13 1101 pc13 * pc136 pc135 pc134 pc133 pc132 pc131 pc130 grayscale palette c13 (13/31) 14 1110 pc14 * pc146 pc145 pc144 pc143 pc142 pc141 pc140 grayscale palette c14 (14/31) 15 1111 pc15 * pc156 pc155 pc154 pc153 pc152 pc151 pc150 grayscale palette c15 (15/31) table7 [2:0] = 111 b ra[3:0] name d7 d6 d5 d4 d3 d2 d1 d0 remark 0 0000 pc16 * pc166 pc165 pc164 pc163 pc162 pc161 pc160 grayscale palette c16 (16/31) 1 0001 pc17 * pc176 pc175 pc174 pc173 pc172 pc171 pc170 grayscale palette c17 (17/31) 2 0010 pc18 * pc186 pc185 pc184 pc183 pc182 pc181 pc180 grayscale palette c18 (18/31) 3 0011 pc19 * pc196 pc195 pc194 pc193 pc192 pc191 pc190 grayscale palette c19 (19/31) 4 0100 pc20 * pc206 pc205 pc204 pc203 pc202 pc201 pc200 grayscale palette c20 (20/31) 5 0101 pc21 * pc216 pc215 pc214 pc213 pc212 pc211 pc210 grayscale palette c21 (21/31) 6 0110 pc22 * pc226 pc225 pc224 pc223 pc222 pc221 pc220 grayscale palette c22 (22/31) 7 0111 pc23 * pc236 pc235 pc234 pc233 pc232 pc231 pc230 grayscale palette c23 (23/31) 8 1000 pc24 * pc246 pc245 pc244 pc243 pc242 pc241 pc240 grayscale palette c24 (24/31) 9 1001 pc25 * pc256 pc255 pc254 pc253 pc252 pc251 pc250 grayscale palette c25 (25/31) 10 1010 pc26 * pc266 pc265 pc264 pc263 pc262 pc261 pc260 grayscale palette c26 (26/31) 11 1011 pc27 * pc276 pc275 pc274 pc273 pc272 pc271 pc270 grayscale palette c27 (27/31) 12 1100 pc28 * pc286 pc285 pc284 pc283 pc282 pc281 pc280 grayscale palette c28 (28/31) 13 1101 pc29 * pc296 pc295 pc294 pc293 pc292 pc291 pc290 grayscale palette c29 (29/31) 14 1110 pc30 * pc306 pc305 pc304 pc303 pc302 pc301 pc300 grayscale palette c30 (30/31) 15 1111 pc31 * pc316 pc315 pc314 pc313 pc312 pc311 pc310 grayscale palette c31 (31/31) NJU6854 -51- ver.2004-06-29 (12) instruction descriptions (12-1) 8-bit access mode (12-1-1) instruction register set msb bit of the 1 st byte to ?0?. data to instruction register is transferred in 2 bytes, for the 1 st byte, d6~d4 is used to set the instruction table address, and d3~d0 to set instruction register address. the 2 nd byte is instruction data. msb lsb 0 instruction table address instruction register address 1 st access data 2 nd access (example) x, y address of ddram step 1: 1 st byte(x address) d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb 0 0 0 0 0 1 0 0 0 1 1 0 step 2: 2 nd byte(x address) d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb xa7 xa6 xa5 xa4 xa3 xa2 xa1 xa0 0 1 1 0 step 3: 1 st byte(y address) d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb 0 0 0 0 0 1 0 1 0 1 1 0 step 4: 2 nd byte(y address). d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb ya7 ya6 ya5 ya4 ya3 ya2 ya1 ya0 0 1 1 0 0 table address register address pins setting 0 pins setting table address register address NJU6854 - 52 - ver.2004-06-29 (12-1-2) auto-increment of instruction register address by setting msb bit of the 1 st byte to ?1?, instruction data can be written to the registers successively. for the 1 st byte, d6~d4 is used to set the instruction table address(table[2:0]) and d3~d0 to set the count number for the registers, from the 2 nd byte, data will be automatically written to the successive registers. msb lsb 1 table address count number(n) data of address 0 count 1 data of address 1 count 2 . . . . . data of address n-1 count n if the counter number is set as 0, data is written to the registers from the address 0 to 15. (example) oscillator and others. step 1: 8bit auto increment / table address set / count number d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb 1 0 0 0 0 1 0 1 0 1 1 0 step 2: 8bit auto increment / count = 1 d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * * * * * crf crs1 crs0 0 1 1 0 step 3: 8 bit auto increment / count = 2 d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb aim1 aim0 vwr idsy idsx win uds swif 0 1 1 0 step 4: 8 bit auto increment / count = 3 d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb vpc7 vpc6 vpc5 vpc4 vpc3 vpc2 vpc1 vpc0 0 1 1 0 step 5: 8 bit auto increment / count = 4 d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * * * * fvc3 fvc2 fvc1 fvc0 0 1 1 0 step 6: 8 bit auto increment / count = 5 d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb xa7 xa6 xa5 xa4 xa3 xa2 xa1 xa0 0 1 1 0 1 table address count number = 5 pins setting NJU6854 -53- ver.2004-06-29 (12-2) 16-bit access mode (12-2-1) instruction register set msb bit to?0?. instruction table number, instruction register address and instruction data will be transferred in one 16-bit data. instruction table number is determined by d14~d12, instruction register is determined by d11~d8, and d7~d0 is instruction data. msb lsb 0 table address register address instruction data (example) x, y address of ddram step 1: x address setting. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 1 0 0 xa7 xa6 xa5 xa4 xa3 xa2 xa1 xa0 step 1: y address setting d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 1 0 1 ya7 ya6 ya5 ya4 ya3 ya2 ya1 ya0 (12-2-2) auto increment of instruction register address by setting msb bit of the 1 st byte to ?1?, instruction data can be written to the registers successively. for the 1 st byte, only upper 8-bit data is valid, d14~d12 is used to set the instruction table number(table[2:0]) and d11~d8 to set the count number of the registers. from the 2 nd byte, data will be automatically written to the successive registers. msb lsb 1 table address count number(n) data of address 0 data of address 1 data of address 2 data of address 3 .. . . .. . . data of address n-2 data of address n-1 if count number is 0, data is written to the registers from the address 0 to 15. (example) oscillator and configuration control step 1: d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 0 0 1 0 1 * * * * * * * * step 2: d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 * * * * * crf crs1 crs0 aim1 aim0 vwr idsy idsx win uds swif step 3: d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 vpc7 vpc6 vpc5 vpc4 vpc3 vpc2 vpc1 vpc0 * * * * fvc3 fvc2 fvc1 fvc0 step 4: d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 xa7 xa6 xa5 xa4 xa3 xa2 xa1 xa0 * * * * * * * * (*: not applicable) 0 data 0 data 1 table address count number = 5 data (don?t care ) table address register address table address register address NJU6854 - 54 - ver.2004-06-29 (12-3) oscillation control register : cr table0 [0 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * * * * * crf crs1 crs0 0 1 1 0 (default: {crf, crs1, crs0} = 0 h , address: 0 h ) setting frequency crf crs1 crs0 function 0 0 0 osci (730 khz) 0 0 1 osc2 (170 khz) 0 1 0 osc5 (external r, external source) 0 1 1 invalid 1 0 0 osc3 (1,200 khz) 1 0 1 osc4 (285 khz) 1 1 0 invalid 1 1 1 invalid in osc5 mode, connect the osci pin and the osco pin with a resistor, and input external clock signal to osci. (12-4) display data assignment/ window area onoff/increment control register: cfg / table 0 [1 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb aim1 aim0 vwr idsy idsx win uds swif 0 1 1 0 (default: {aim1, aim0, vwr, idsy, isdx, win, uds, swif} = 0 h , address: 1 h ) (i) swif swif bus length 0 8bit i/f (initial value) 1 16bit i/f (ii) uds assignment of mpu data on the ddram 16 bit i/f access uds = ?0?: the lower 8-bit mpu data corresponding to the lower 8-bit display data the upper 8-bit mpu data corresponding to the upper 8-bit display data uds = ?1?: the lower 8-bit mpu data corresponding to the upper 8-bit display data the upper 8-bit mpu data corresponding to the lower 8-bit display data 8 bit i/f access uds = ?0?: 1 st mpu data corresponding to the lower 8-bit display data 2 nd mpu data corresponding to the upper 8-bit display data uds = ?1?: 1 st mpu data corresponding to the upper 8-bit display data 2 nd mpu data corresponding to the lower 8-bit display data (iii) win win = ?1? : window area on win = ?0? : window area off(default) (iv) idsx x address auto increment/auto decrement idsx = ?0? : auto increment idsx = ?1? : auto decrement (v) idsy y address auto increment/auto decrement idsy = ?0? : auto increment idsy = ?1? : auto decrement NJU6854 -55- ver.2004-06-29 (vi) vwr setting the direction of data write /read to ddram vwr = ?0? : start from x direction vwr = ?1? : start from y direction (vii) aim[1:0] aim1 aim0 0 0 auto increment/decrement during data writing and reading 0 1 auto increment/decrement during data writing 1 0 auto increment/decrement off 1 1 prohibited (12-5) display line number register: vpc table0 [2 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb vpc7 vpc6 vpc5 vpc4 vpc3 vpc2 vpc1 vpc0 0 1 1 0 (default: vpc[7:0] = 84 h , address: 2 h ) vpc[7:0]: display line number (displayed pixel number in y direction). setting within the range of 2~132 02h~84h vpc7 vpc6 vpc5 vpc4 vpc3 vpc2 vpc1 vpc0 vertical pixel number 0 0 0 0 0 0 0 0 forbidden 0 0 0 0 0 0 0 1 forbidden 0 0 0 0 0 0 1 0 2 0 0 0 0 0 0 1 1 3 0 0 0 0 0 1 0 0 4 0 0 0 0 0 1 0 1 5 : 1 0 0 0 0 0 1 0 130 1 0 0 0 0 0 1 1 131 1 0 0 0 0 1 0 0 132 1 0 0 0 0 1 0 1 forbidden : 1 1 1 1 1 1 1 1 forbidden (12-6) blank line number register : fvc table0 [3 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * * * * fvc3 fvc2 fvc1 fvc0 0 1 1 0 (default: fvc[3:0]=0 h , address: 3 h ) fvc[3:0]: blank line number(not displayed pixel number in y direction) fvc3 fvc2 fvc1 fvc0 vertical blanking lines 0 0 0 0 0 0 0 0 1 1 : 1 1 1 0 14 1 1 1 1 15 NJU6854 - 56 - ver.2004-06-29 (12-7) x address register : adrh table0 [4 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb xa7 xa6 xa5 xa4 xa3 xa2 xa1 xa0 0 1 1 0 (default: xa[7:0] = 0h, address: 4h) x address range is from 00h to 83h. (12-8) y address register : adrl table0 [5 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb ya7 ya6 ya5 ya4 ya3 ya2 ya1 ya0 0 1 1 0 (default: ya[7:0] = 0 h , address: 5 h ) y address range is from 00h to 83h. (12-9) window end x address register : eadrh table0 [6 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb xea7 xea6 xea5 xea4 xea3 xea2 xea1 xea0 0 1 1 0 (default: xea[7:0] = 0 h , address: 6 h ) setting x address of window area when window area access is valid(win=?1?). (12-10) window end y address register : eadrl table0 [7h] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb yea7 yea6 yea5 yea4 yea3 yea2 yea1 yea0 0 1 1 0 (default: yea[7:0] = 0 h , address: 7 h ) setting y address of window area when window area access is valid(win=?1?). (12-11) display mode/grayscale mode register : color table0 [8 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb pwmm1 pwmm0 * mode1 mode0 * * moded 0 1 1 0 (default: pwmm[1:0], mode[1:0], moded = 0 h , address: 8 h ) (i) moded setting 65k-color or 4k-color display mode moded display color mode 0 65,536 colors mode (pwm 5bit + 2 frc) 1 4,096 colors(4bit pwm only) (ii) mode[1:0] bit assignment of display data mode[1:0] input data mode1 mode0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 remark 0 0 c4 c3 c2 c1 c0 b5 b4 b3 b2 b1 b0 a4 a3 a2 a1 a0 note (1) 0 1 c3 c2 c1 c0 b3 b2 b1 b0 a3 a2 a1 a0 note (2) 1 0 c3 c2 c1 c0 b3 b2 b1 b0 a3 a2 a1 a0 note (3) 1 1 invalid note (1) 65,536 colors 5-6-5 data (2) 4,096 colors 4-4-4 data (3) 4,096 colors4-4-4 data, upper 4 bits invalid NJU6854 -57- ver.2004-06-29 (iii) pwmm[1:0] setting grayscale mode through pwm control. pwmm1 pwmm0 grayscale mode 0 0 select 32 grayscales 65k mode or 16 grayscales 4k mode from 64 levels. 0 1 select 32 grayscales 65k mode or 16 grayscales 4k mode from 32 levels. 1 0 select 16 grayscales 4k mode from 16 levels. 1 1 select 32 grayscales 65k mode or 16 grayscales 4k mode from 128 levels. using pwm control (pwmm[1:0]) and frame rate control(frc), the following display mode can be selected. pwm control moded display mode frc control 64 grayscales base 32 grayscales base 16 grayscales base 128 grayscales base 0 65,536 color mode 2 scan 32 grayscales selectable 32grayscales selectable forbidden 32 grayscales selectable 1 4,096 color mode unavailable 16 grayscales selectable 16 grayscales selectable 16 grayscales selectable 16 grayscales selectable the relationship among the oscillating circuit, built-in clock and frame frequency original source clock osci,osc2,osc3,osc4,osc5(external) selection crf,crs[1:0] register internal oscillator resistor selection(0.7~1.3xr) crb[2:0] register gck(source clock for grayscale signal) signal generator frequency dividing ratio selection (1/1~1/8) mdiv[2:0] register gck bckg lp(latch pulse) signal generator decided by dividing rate(1/127,63,31,15) pwmm[1:0], moded lp bckg lp duty set selection one decided by vpc or (ppc1+ppc2) or (ppc1+ppc2+ppc3) : 1/2~1/132 vpc,ppc1,ppc2,ppc3 vertical blanking line set number of inserted lp pulse(0~15) fvc[3:0] flm source clock for dcdc booster booster clock making bck[3:0] booster clock fig 17 block diagram of oscillator frame duty = 1 / (duty + blank) osc mdiv 1/127,63,31,15 1/duty + blank flm lp booster clock bck bcks fvc[3:0] bcks pwmm[1:0] vpc, ppc1,ppc2,ppc3 bck[3:0] crb[2:0] crf crs[1:0] mdiv[2:0] 0 1 gck bckg bckg 0 1 ckcont 1/8 osc mdiv 1/127,63,31,15 1/duty + blank flm lp booster clock bck bcks fvc[3:0] bcks pwmm[1:0] vpc, ppc1,ppc2,ppc3 bck[3:0] crb[2:0] crf crs[1:0] mdiv[2:0] 0 1 gck bckg bckg 0 1 ckcont 1/8 NJU6854 - 58 - ver.2004-06-29 pwm duty vs. display mode pwm control pwmm=00 pwmm=01 pwmm=10 pwmm=11 display mode moded variable variable fixed variable 65,536 color mode 0 1/63 1/31 forbidden 1/127 4,096 color mode 1 1/63 1/31 1/15 1/127 frame frequency vs. display mode usage oscillator gck display mode grayscale mode ( pwmm[1:0] ) duty blank equation *1) 0 flm=1200khz/(1x127x(132+ 0))=72hz 1 1200 khz 1/1 undivided 65,536 color variable among 128 1/132 5 flm=1200khz/(1x127x(132+ 5))=69hz 0 flm=285khz/(1x31x(132+ 0))=70hz 2 285 khz 1/1 undivided 4,096 color variable among 32 1/132 10 flm=285khz/(1x31x(132+10))=65hz 0 flm=170khz/(1x15x(132+ 0))=86hz 3 170 khz 1/1 undivided 4,096 color fixed among 32 1/132 15 flm=170khz/(1x15x(132+15))=77hz 0 flm=730khz/(1x63x(132+ 0))=88hz 4 730 khz 1/1 undivided 65,536 color variable among 64 1/132 8 flm=730khz/(1x63x(132+ 8))=83hz note): flm: frame frequency = f osc / (mdiv(1,2,3,4,5,6,7,8) x pwmm(15,31,63,127) x (duty + blank)) NJU6854 -59- ver.2004-06-29 65k colors display mode display data and grayscale palette. note1) 5 bits for pwm control and 1 bit for frame rate control(total 6 bits display data), segbi can realize 64-grayscale (32-grayscalex2) display. note2) real 64-grayscael can be realized by setting pbx bit(gs=?0?). display ram data grayscale by pwm + frc a4 a3 a2 a1 a0 - a/c b c/a b5 b4 b3 b2 b1 b0 32 gray 64 gray (1) 32 gray c4 c3 c2 c1 c0 - gs=x gs=1 gs=0 gs=x 0 0 0 0 0 0 pb0 pb0 0 0 0 0 0 1 pa0 pb0 pbx pc0 0 0 0 0 1 0 ( pb0 + pb1 ) / 2 ( pb0 + pb1 ) / 2 0 0 0 0 1 1 pa1 pb1 pb1 pc1 0 0 0 1 0 0 ( pb1 + pb2 ) / 2 ( pb1 + pb2 ) / 2 0 0 0 1 0 1 pa2 pb2 pb2 pc2 0 0 0 1 1 0 ( pb2 + pb3 ) / 2 ( pb2 + pb3 ) / 2 0 0 0 1 1 1 pa3 pb3 pb3 pc3 0 0 1 0 0 0 ( pb3 + pb4 ) / 2 ( pb3 + pb4 ) / 2 0 0 1 0 0 1 pa4 pb4 pb4 pc4 0 0 1 0 1 0 ( pb4 + pb5 ) / 2 ( pb4 + pb5 ) / 2 0 0 1 0 1 1 pa5 pb5 pb5 pc5 0 0 1 1 0 0 ( pb5 + pb6 ) / 2 ( pb5 + pb6 ) / 2 0 0 1 1 0 1 pa6 pb6 pb6 pc6 0 0 1 1 1 0 ( pb6 + pb7 ) / 2 ( pb6 + pb7 ) / 2 0 0 1 1 1 1 pa7 pb7 pb7 pc7 0 1 0 0 0 0 ( pb7 + pb8 ) / 2 ( pb7 + pb8 ) / 2 0 1 0 0 0 1 pa8 pb8 pb8 pc8 0 1 0 0 1 0 ( pb8 + pb9 ) / 2 ( pb8 + pb9 ) / 2 0 1 0 0 1 1 pa9 pb9 pb9 pc9 0 1 0 1 0 0 ( pb9 + pb10 ) / 2 ( pb9 + pb10 ) / 2 0 1 0 1 0 1 pa10 pb10 pb10 pc10 0 1 0 1 1 0 ( pb10 + pb11 ) / 2 ( pb10 + pb11 ) / 2 0 1 0 1 1 1 pa11 pb11 pb11 pc11 0 1 1 0 0 0 ( pb11 + pb12 ) / 2 ( pb11 + pb12 ) / 2 0 1 1 0 0 1 pa12 pb12 pb12 pc12 0 1 1 0 1 0 ( pb12 + pb13 ) / 2 ( pb12 + pb13 ) / 2 0 1 1 0 1 1 pa13 pb13 pb13 pc13 0 1 1 1 0 0 ( pb13 + pb14 ) / 2 ( pb13 + pb14 ) / 2 0 1 1 1 0 1 pa14 pb14 pb14 pc14 0 1 1 1 1 0 ( pb14 + pb15 ) / 2 ( pb14 + pb15 ) / 2 0 1 1 1 1 1 pa15 pb15 pb15 pc15 1 0 0 0 0 0 ( pb15 + pb16 ) / 2 ( pb15 + pb16 ) / 2 1 0 0 0 0 1 pa16 pb16 pb16 pc16 1 0 0 0 1 0 ( pb16 + pb17 ) / 2 ( pb16 + pb17 ) / 2 1 0 0 0 1 1 pa17 pb17 pb17 pc17 1 0 0 1 0 0 ( pb17 + pb18 ) / 2 ( pb17 + pb18 ) / 2 1 0 0 1 0 1 pa18 pb18 pb18 pc18 1 0 0 1 1 0 ( pb18 + pb19 ) / 2 ( pb18 + pb19 ) / 2 1 0 0 1 1 1 pa19 pb19 pb19 pc19 1 0 1 0 0 0 ( pb19 + pb20 ) / 2 ( pb19 + pb20 ) / 2 1 0 1 0 0 1 pa20 pb20 pb20 pc20 1 0 1 0 1 0 ( pb20 + pb21 ) / 2 ( pb20 + pb21 ) / 2 1 0 1 0 1 1 pa21 pb21 pb21 pc21 1 0 1 1 0 0 ( pb21 + pb22 ) / 2 ( pb21 + pb22 ) / 2 1 0 1 1 0 1 pa22 pb22 pb22 pc22 1 0 1 1 1 0 ( pb22 + pb23 ) / 2 ( pb22 + pb23 ) / 2 1 0 1 1 1 1 pa23 pb23 pb23 pc23 1 1 0 0 0 0 ( pb23 + pb24 ) / 2 ( pb23 + pb24 ) / 2 1 1 0 0 0 1 pa24 pb24 pb24 pc24 1 1 0 0 1 0 ( pb24 + pb25 ) / 2 ( pb24 + pb25 ) / 2 1 1 0 0 1 1 pa25 pb25 pb25 pc25 1 1 0 1 0 0 ( pb25 + pb26 ) / 2 ( pb25 + pb26 ) / 2 1 1 0 1 0 1 pa26 pb26 pb26 pc26 1 1 0 1 1 0 ( pb26 + pb27 ) / 2 ( pb26 + pb27 ) / 2 1 1 0 1 1 1 pa27 pb27 pb27 pc27 1 1 1 0 0 0 ( pb27 + pb28 ) / 2 ( pb27 + pb28 ) / 2 1 1 1 0 0 1 pa28 pb28 pb28 pc28 1 1 1 0 1 0 ( pb28 + pb29 ) / 2 ( pb28 + pb29 ) / 2 1 1 1 0 1 1 pa29 pb29 pb29 pc29 1 1 1 1 0 0 ( pb29 + pb30 ) / 2 ( pb29 + pb30 ) / 2 1 1 1 1 0 1 pa30 pb30 pb30 pc30 1 1 1 1 1 0 ( pb30 + pb31 ) / 2 ( pb30 + pb31 ) / 2 1 1 1 1 1 1 pa31 pb31 pb31 pc31 NJU6854 - 60 - ver.2004-06-29 4k colors display mode display data and grayscale palette. display ram data grayscale by pwm a3 a2 a1 a0 a / c b c / a b3 b2 b1 b0 16 gray 16 gray 16 gray c3 c2 c1 c0 gs=x gs=x gs=x 0 0 0 0 pa1 pb1 pc1 0 0 0 1 pa3 pb3 pc3 0 0 1 0 pa5 pb5 pc5 0 0 1 1 pa7 pb7 pc7 0 1 0 0 pa9 pb9 pc9 0 1 0 1 pa11 pb11 pc11 0 1 1 0 pa13 pb13 pc13 0 1 1 1 pa15 pb15 pc15 1 0 0 0 pa17 pb17 pc17 1 0 0 1 pa19 pb19 pc19 1 0 1 0 pa21 pb21 pc21 1 0 1 1 pa23 pb23 pc23 1 1 0 0 pa25 pb25 pc25 1 1 0 1 pa27 pb27 pc27 1 1 1 0 pa29 pb29 pc29 1 1 1 1 pa31 pb31 pc31 note) under 4k colors display mode, gs bit is invalid. (12-12) oscillating frequency adjustment/frequency dividing register : mdiv table0 [9h] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * mdiv2 mdiv1 mdiv0 * crb2 crb1 crb0 0 1 1 0 (default: mdiv[2:0], crb[2:0] = 0h, address : 9h) (i) crb[2:0] frame frequency can be modified by adjusting the resistor of oscillating circuit. relationship between rf and resistance ratio (ii) mdiv[2:0] oscillating frequency or external clock frequency can be divided. mdiv2 mdiv1 mdiv0 divide ratio 0 0 0 1/1 dividing 0 0 1 1/2 dividing 0 1 0 1/3 dividing 0 1 1 1/4 dividing 1 0 0 1/5 dividing 1 0 1 1/6 dividing 1 1 0 1/7 dividing 1 1 1 1/8 dividing crb2 crb1 crb0 status 0 0 0 initial resistance ratio 0 0 1 1.1 times of initial resistance ratio 0 1 0 1.2 times of initial resistance ratio 0 1 1 1.3 times of initial resistance ratio 1 0 0 0.9 times of initial resistance ratio 1 0 1 0.8 times of initial resistance ratio 1 1 0 0.7 times of initial resistance ratio 1 1 1 forbidden NJU6854 -61- ver.2004-06-29 (12-13) header com register : hct table0 [a h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * hct6 hct5 hct4 hct3 hct2 hct1 hct0 0 1 1 0 (default: hct [6:0] = 0 h , address: a h ) for small panel size(row number is less than 132), this instruction is used to decide header com position to specify available com drivers. the setting range is from coma0/comb0 ~ coma65/comb65. refer to ?(13) relationship between logic com number and physical com driver? for details. note that this instruction is not used to specify a scan start position, the scan start position is decided by the ?scan start com 1~3?. 0 hct (132-vpc)/2 hct6 hct5 hct4 hct3 hct2 hct1 hct0 header com 0 0 0 0 0 0 0 coma0/comb0 0 0 0 0 0 0 1 coma1/comb1 0 0 0 0 0 1 0 coma2/comb2 0 0 0 0 0 1 1 coma3/comb3 0 0 0 0 1 0 0 coma4/comb4 0 0 0 0 1 0 1 coma5/comb5 0 1 1 1 1 1 0 coma62/comb62 0 1 1 1 1 1 1 coma63/comb63 1 0 0 0 0 0 0 coma64/comb64 1 0 0 0 0 0 1 coma65/comb65 1 0 0 0 0 1 0 forbidden 1 1 1 1 1 1 1 forbidden (12-14) initial display line register : hst table0 [bh] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb hst7 hst6 hst5 hst4 hst3 hst2 hst1 hst0 0 1 1 0 (default : hst[7:0] = 0 h , address: b h ) this instruction sets the ddram y address, and the addressed ram data will be displayed by the scan start com 1 driver. the available y address range is from 0~131. hst7 hst6 hst5 hst4 hst3 hst2 hst1 hst0 y address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 2 0 0 0 0 0 0 1 1 3 0 0 0 0 0 1 0 0 4 0 0 0 0 0 1 0 1 5 : 0 1 1 1 1 1 1 0 128 0 1 1 1 1 1 1 1 129 1 0 0 0 0 0 0 0 130 1 0 0 0 0 0 1 1 131 1 0 0 0 0 1 0 0 forbidden 1 1 1 1 1 1 1 1 forbidden NJU6854 - 62 - ver.2004-06-29 (12-15) scan start com 1 register : ssc1 table0 [ch] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb ssc17 ssc16 ssc15 ssc14 ssc13 ssc12 ssc11 ssc10 0 1 1 0 (default : ssc1[7:0] = 0 h , address: c h ) totally three partial area can be display on the screen once time. this instruction sets the logical number of the scan start com driver for the full screen display or for the first partial display. refer to (13) relationship between logical com number and physical com driver for details. the available setting range is: 0 ssc1 (vpc ? 1) (12-16) scan start com 2 register : ssc2 table0 [dh] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb ssc27 ssc26 ssc25 ssc24 ssc23 ssc22 ssc21 ssc20 0 1 1 0 (default : ssc2[7:0] = 0 h , address: d h ) this instruction sets the logical number of the scan start com driver for the second partial display. refer to (13) relationship between logical com number and physical com driver for details. the available setting range is: ssc1+pcc1 ssc2 (vpc ? 1) (12-17) line number of partial display 1 register : pcc1 table0 [eh] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb pcc17 pcc16 pcc15 pcc14 pcc13 pcc12 pcc11 pcc10 0 1 1 0 (default : pcc1[7:0] = 0 h , address: e h ) this instruction sets line number(ddram y address range) for the first partial display. in the partial display mode, this instruction has priority over the display line number(vpc) setting. pcc1+pcc2+pcc3 will be the display duty. the available setting range is: 0 pcc1 (vpc - ssc1) (12-18) line number of partial display 2 register : pcc2 table0 [fh] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb pcc27 pcc26 pcc25 pcc24 pcc23 pcc22 pcc21 pcc20 0 1 1 0 (default : pcc2[7:0] = 0 h , address: f h ) this instruction sets line number(ddram y address range) for the second partial display. in the partial display mode, this instruction has priority over the display line number(vpc) setting. pcc1+pcc2+pcc3 will be the display duty. the available setting range is: 0 pcc2 (vpc ? ssc2). (12-19) n-line inversion register : mc table1 [0h] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb mc7 mc6 mc5 mc4 mc3 mc2 mc1 mc0 0 1 1 0 (default : mc[7:0] = 0 h , address: 0 h ) this instruction can let lcd driving signal polarity (m signal) to be alternated every n(2= NJU6854 - 64 - ver.2004-06-29 (iv) b[2:0] lcd bias ratio b2 b1 b0 function 0 0 0 1/5 bias 0 0 1 1/6 bias 0 1 0 1/7 bias 0 1 1 1/8 bias 1 0 0 1/9 bias (initial state) 1 0 1 1/10 bias 1 1 0 1/11 bias 1 1 1 1/12 bias (12-21) electronic volume control register: evol table1 [2h] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * evol6 evol5 evol4 evol3 evol2 evol1 evol0 0 1 1 0 (default: evol[6:0] = 0 h , address: 2 h ) 128 steps available evol6 evol5 evol4 evol3 evol2 evol1 evol0 output voltage 0 0 0 0 0 0 0 lower 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 higher v reg can be calculated from the equation (1) v reg = v ref x n ..............................................................................................................(1) (n determined by vu[2:0](boost level), rg[2:0] and gsel bits of gvu register) lcd driving voltage v 0 can be calculated from the equation (2) v0 = 0.5 x v reg + m x (v reg ? 0.5 v reg ) / 127 ??????......?? ?????.(2) (electronic volume m determined by evol[6:0] bits of evol register) (12-22) display timing signal monitor/pbx palette register : pbx table1 [3h] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb mon * * gs pbx3 pbx2 pbx1 pbx0 0 1 1 0 (default: mon, gs = 0 h , pbx[3:0] = 3 h , address: 3 h ) (i) mon setting flm, lp and m signals output on/off mon function 0 flm, lp, m signal output off default 1 flm, lp, m signal output on (ii) gs, pbx[3:0] when gs=?0?, palette pbx setting is available. when gs=?1?, pb0 is selected. gs=1 pbx[3:0] register invalid gs=0 0 0 0 pbx3 pbx2 pbx1 pbx0 (note 1) note 1) under 65k colors mode , palette pbx is selected to set b data. pbx is used to display the grayscale between pb0 and pb1. NJU6854 -65- ver.2004-06-29 (12-23) power control 2 register : pow2 table1 [5h] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * * * ckcont ampon halt dcon res 0 1 1 0 (default: ckcont, ampon, halt, dcon, res = 0 h , address: 5 h ) (i) res res = ?0?: default res = ?1?: initialization note 1) after initialization(res=?1?), res bit turn to ?0?. note 2) after initialization, at least two lp signal cycles is needed to wait to execute the next instruction. (ii) dcon setting voltage booster on/off. dcon= ?0?: voltage booster off dcon= ?1?: voltage booster on (iii) halt setting power save mode on/off halt = ?0?: power save mode off(default) halt = ?1?: power save mode on lsi internal status under power save mode: a. internal oscillator and lcd power supply is in the halted state. b. com/seg outputs v ssh level voltage. c. external clock is unacceptable. d. ddram data is remained e. instruction register data is remained (iv) ampon using together with vgoff and vbon bits of power control 1register (tcbi) to set voltage converter on/off. ampon = ?0? voltage converter off ampon = ?1?: voltage converter on (v) ckcont setting gck signal and lp signal on/off ckcont = ?0?: gck and lp off ckcont = ?1?: gck and lp on note) NJU6854 use internal oscillator or external clock signal to generate gck and lp signal. not only used as display clock, gck and lp are also used as operating clock for voltage booster. be sure to set ckcont=?1? when voltage booster is used(dcon= ?1?). NJU6854 - 66 - ver.2004-06-29 (12-24) booster level/amplifier gain register : gvu table1 [6h] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb gsel rg2 rg1 rg0 * vu2 vu1 vu0 0 1 1 0 (default: gsel, rg[2:0] = 0h, vu[2:0] = 0h, address: 6h) (i) gsel setting amplifier gain of vreg gsel = 0: amplifier gain is determined by vu[2:0] bits as the same as the boost level. gsel = 1: amplifier gain is determined by rg[2:0] bits (ii)rg[2:0] when gsel=?1?, the relationship between rg[2:0] and amplifier gain is showed as below. gsel = ?0? gsel = ?1? vu2 vu1 vu0 rg2 rg1 rg0 amplifier gain (n) remark 0 0 0 - default vu[2:0] 0 0 1 2 0 1 0 0 0 0 3 default rg[2:0] 0 1 1 0 0 1 4 1 0 0 0 1 0 5 1 0 1 0 1 1 6 1 0 0 6.45 1 0 1 7 1 1 0 7.3 1 1 1 8.0 1 1 0 - 1 1 1 - (iii) vu[2:0] setting boost level. and when gsel=?0?, also setting amplifier gain of v reg. vu2 vu1 vu0 function 0 0 0 no boost up 0 0 1 2 times boost up 0 1 0 3 times boost up 0 1 1 4 times boost up 1 0 0 5 times boost up 1 0 1 6 times boost up 1 1 0 forbidden 1 1 1 forbidden NJU6854 -67- ver.2004-06-29 (12-25) voltage booster clock register : bck table1 [7h] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb bcks bckg * * bck3 bck2 bck1 bck0 0 1 1 0 (default: bcks, bckg, bck[3:0] = 0 h , address: 7 h ) note) NJU6854 use internal oscillator or external clock to generate gck and lp signal. not only used as display clock, gck and lp are also used as operating clock for voltage booster. be sure to set ckcont=?1? when voltage booster is used(dcon= ?1?). (i) bck[3:0] setting dividing ratio for the oscillating signal or external clock to generate gck and lp. bck3 bck2 bck1 bck0 function 0 0 0 0 1/1 dividing (there is a restriction) 0 0 0 1 1/2 dividing 0 0 1 0 1/3 dividing 0 0 1 1 1/4 dividing 0 1 0 0 1/5 dividing 1 0 1 1 1/12 dividing 1 1 0 0 1/13 dividing 1 1 0 1 1/14 dividing 1 1 1 0 1/15 dividing 1 1 1 1 1/16 dividing note) when bck[3:0]=[0000, mdiv[2:0]=[000] and bcks=?1? settings are prohibited. (ii) bckg when bckg=?1?, mdiv output signal is equally divided into 8 time slots. (iii) bcks selecting divided clock signal. bcks = ?0? : lp signal bcks = ?1? : bckg signal note) there is a trade-off relationship between voltage booster driving capability and current consumption, so the optimal booster clock shall be decided by your lcd module. NJU6854 - 68 - ver.2004-06-29 (12-26) display control register : display table1 [8h] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb ref swap * shift1 shift0 tbc ten on/off 0 1 1 0 (default: ref, swap, shift[1:0], tbc, ten, on/off = 0 h , address: 8 h ) (i) on/off display control on/off on/off = ?0?: display off on/off = ?1?: display on (ii) ten ten = ?0?: normal ten = ?1?: independent from ddram data, pixels are forced to be on or off. (iii) tbc(ten = ?1?) tbc = ?0? : all pixels on tbc = ?1? : all pixels off (iv) shift[1:0] setting the shift direction of the com drivers? output. (v) swap switching corresponding relationship between ddram data and palette a, b, c. this bit shall be set before ddram data writing. swap = ?0?: normal swap = ?1?: swap (vi) ref reversing the shift direction of seg drivers? output by redirecting x address. this bit shall be set before ddram data writing. ref = ?0?: normal ref = ?1?: opposite direction NJU6854 -69- ver.2004-06-29 (12-27) pwm control register : pwm table1 [9h] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * * pwmc1 pwmc0 pwmb1 pwmb0 pwma1 pwma0 0 1 1 0 (default: pwmc[1:0], pwmb[1:0],pwma[1:0] = 0 h , address: 9 h ) (i) pwmc[1:0], pwmb[1:0], pwma[1:0] setting pwm signals for sega, segb, and segc respectively. segai (i=0~131) pwma1 pwma0 output timing 0 0 forward pwm 0 1 backward pwm 1 0 forward and backward alternately 1 1 shift phase segbi (i=0~131) pwmb1 pwmb0 output timing 0 0 forward pwm 0 1 backward pwm 1 0 forward and backward alternately 1 1 shift phase segci (i=0~131) pwmc1 pwmc0 output timing 0 0 forward pwm 0 1 backward pwm 1 0 forward and backward alternately 1 1 shift phase m shift phase forward and backward alternatively backward forward lp NJU6854 - 70 - ver.2004-06-29 (12-28) three partial display areas/ led driver control/rev bit register : econt table1 [ah] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb tst0 en3ptl enled rev led13 led12 led11 led10 0 1 1 0 (default: tst0, en3ptl, enled, rev, led1[3:0] = 0 h , address: a h ) (i) tst0 for maker testing, usually set to ?0?. (ii) en3ptl when en3ptl=?1?, three specified partial areas can be displayed through setting ssc1[7:0]~ssc3[7:0] and pcc1[7:0]~pcc3[7:0]. if setting en3ptl=?0?, one or two partial area can be displayed. (iii) enled when enled=?1?, data saved at led1[3:0] can be used to control white led through control port(ldat, lsck, lreq, lresb) enled = 0 : ldat, lsck, lreq, lresb ports invalid (high impedance) enled = 1 : ldat, lsck, lreq, lresb ports valid. (iv) led1 [3:0] when enled=?1?, white led control ports (ldat, lsck, lreq, lresb) are valid, led control signal output from ldat, lsck, lreq and lresb to led10, led11, led12 and led13 respectively. concerning white led driver, please refer to njrc white led controller series (nju6051/52/53). besides, the above mentioned bits and ports can be used as general-purpose ports too. note) for njrc white led driver, data pin state will be changed according to request pin. when request pin is ?l?, data pin of white led driver is in input state, and when request pin is ?h?, data pin become output state. when lreq pin of NJU6854 is ?l?, ldat pin output signals, and when lreq is ?h?, ldat is in input state. so, if ldat, lsck, lreq and lresb are used as common ports, please pay attention to this point. lsck, lreq and lresb pins can be used as 3-bit general-purpose ports too. example of connection with nju6053 timing sequence of data sending nju6053 rstb req sck data NJU6854 lresb lreq lsck ldat nju6053 rstb req sck data NJU6854 lresb lreq lsck ldat b7 b6 b5 b1 b0 lresb lreq lsck ldat b7 b6 b5 b1 b0 b7 b6 b5 b1 b0 lresb lreq lsck ldat b7 b6 b5 b1 b0 NJU6854 -71- ver.2004-06-29 timing sequence of data receiving follow chart of nju6053 operation (v) rev without changing data in ddram, pixel display state can be inverted rev = ?0?: data=?1? pixel on (normal) rev = ?1?: data=?0? pixel on (reversed) b7 b6 b5 b1 b0 lresb lreq lsck ldat b7 b6 b5 b1 b0 b7 b6 b5 b1 b0 lresb lreq lsck ldat b7 b6 b5 b1 b0 initialization of nju6053 (lresb=l->h) ?0?-> led13 o r ?1? ->led1 3 data sending request active (lreq=l) ?0?-> led12 data setting(ldat=data(7)) data(7th bit) -> led10 clock setting(lsck=l->h) ?0? ->led11 or ?1? -> led11 data setting (ldat=data(0)) data(0 bit) -> led10 clock setting (lsck=l->h) ?0? -> led11 or ?1? -> led11 data receiving request active (lreq=h) ? 1 ?-> led12 clock setting (lsck=l->h) ?0? -> led11 or ?1? -> led11 edata read clock setting (lsck=l->h) ?0? -> led11 or ?1? -> led11 cycle 8 times data 6 ~ 1 sen t under the same wa y data sending data receiving in instruction data read, edata is read out NJU6854 - 72 - ver.2004-06-29 (12-29) discharge on/off register : dis table1 [bh] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * * * * * * dis2 dis1 0 1 1 0 (default: dis[2:1] = 0 h , address: b h ) (i) dis1 if dis1=?1?, the capacitors connected to v 0 ~v 4 pins discharge. dis1 = ?0?: discharge off dis1 = ?1?: discharge on (ii) dis2 if dis2=?1?, the capacitor connected to v out pin discharge dis2 = ?0?: discharge off dis2 = ?1?: discharge on (12-30) led driver data register : edata table1 [ch] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb led27 led26 led25 led24 led23 led22 led21 led20 0 1 1 0 (default: led2[7:0] = 0 h , address: c h ) (i)led2[7:0] data from njrc white led driver(nju6051/52/53) is saved in this register. (12-31) instruction table/address register : ra table1 [dh] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb rss ra6 ra5 ra4 ra3 ra2 ra1 ra0 0 1 1 0 (default: ra[6:0] = 0 h , address: d h ) ra[6:4] : instruction table selection ra6 ra5 ra4 table indicator 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 v 0 dis1 v1 v2 v3 v4 v ssh v 0 dis1 v1 v2 v3 v4 v ssh 5m(typ) 100k(typ) vout v ee dis2 NJU6854 -73- ver.2004-06-29 ra[3:0] :register address selection during direct access, or increment number selection in auto increment mode. ra3 ra2 ra1 ra0 direct access (address selection) auto increment setting increment number 0 0 0 0 0 h 1 0 0 0 1 1 h 2 0 0 1 0 2 h 3 0 0 1 1 3 h 4 0 1 0 0 4 h 5 0 1 0 1 5 h 6 0 1 1 0 6 h 7 0 1 1 1 7 h 8 1 0 1 1 b h 12 1 1 0 0 c h 13 1 1 0 1 d h 14 1 1 1 0 e h 15 1 1 1 1 f h 0 rss: rss = ?1?: increment number in auto increment mode. rss = ?0?: register address selection for direct access (12-32) scan start com 3 register : ssc3 table1 [eh] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb ssc37 ssc36 ssc35 ssc34 ssc33 ssc32 ssc31 ssc30 0 1 1 0 (default: ssc3[7:0] = 0 h , address: e h ) this instruction sets the logical number of the scan start com driver for the third partial display, and the setting method just as of the scan start com 1 or 2. this instruction can not be used with normal display and single partial display. when en3ptl = ?1?, the setting is valid. range: ssc2 + pcc2 ssc3 (vpc ? 1) (12-33) line number of partial display 3 register : pcc3 table1 [fh] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb pcc37 pcc36 pcc35 pcc34 pcc33 pcc32 pcc31 pcc30 0 1 1 0 (default: pcc3[7:0] = 0 h , address: f h ) this instruction set line number(ddram y address range) for the third partial display area. in the partial display mode, this instruction has priority over the display line number(vpc) setting. pcc1+pcc2+pcc3 will be the display duty. when en3ptl = ?1?, the setting is valid range: 0 pcc3 (vpc ? ssc3) NJU6854 - 74 - ver.2004-06-29 (12-34) grayscale palette (pa0~pa31, pb0~pb31, pc0~pc31) register : pa0 table2 [0 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa06 pa05 pa04 pa03 pa02 pa01 pa00 0 1 1 0 (initialization: pa0[6:0] = 0 h , register address: 0 h ) register : pa1 table2 [1 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa16 pa15 pa14 pa13 pa12 pa11 pa10 0 1 1 0 (initialization: pa1[6:0] = 6 h , register address: 1 h ) register : pa2 table2 [2 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa26 pa25 pa24 pa23 pa22 pa21 pa20 0 1 1 0 (initialization: pa2[6:0] = a h , register address: 2 h ) register : pa3 table2 [3 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa36 pa35 pa34 pa33 pa32 pa31 pa30 0 1 1 0 (initialization: pa3[6:0] = e h , register address: 3 h ) register : pa4 table2 [4 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa46 pa45 pa44 pa43 pa42 pa41 pa40 0 1 1 0 (initialization: pa4[6:0] = 12 h , register address: 4 h ) register : pa5 table2 [5 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa56 pa55 pa54 pa53 pa52 pa51 pa50 0 1 1 0 (initialization: pa5[6:0] = 16 h , register address: 5 h ) register : pa6 table2 [6 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa66 pa65 pa64 pa63 pa62 pa61 pa60 0 1 1 0 (initialization: pa6[6:0] = 1a h , register address: 6 h ) register : pa7 table2 [7 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa76 pa75 pa74 pa73 pa72 pa71 pa70 0 1 1 0 (initialization: pa7[6:0] = 1e h , register address: 7 h ) register : pa8 table2 [8 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa86 pa85 pa84 pa83 pa82 pa81 pa80 0 1 1 0 (initialization: pa8[6:0] = 22 h , register address: 8 h ) register : pa9 table2 [9 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa96 pa95 pa94 pa93 pa92 pa91 pa90 0 1 1 0 (initialization: pa9[6:0] = 26 h , register address: 9 h ) register : pa10 table2 [a h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa106 pa105 pa104 pa103 pa102 pa101 pa100 0 1 1 0 (initialization: pa10[6:0] = 2a h , register address: a h ) NJU6854 -75- ver.2004-06-29 register : pa11 table2 [b h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa116 pa115 pa114 pa113 pa112 pa111 pa110 0 1 1 0 (initialization: pa11[6:0] = 2e h , register address: b h ) register : pa12 table2 [c h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa126 pa125 pa124 pa123 pa122 pa121 pa120 0 1 1 0 (initialization: pa12[6:0] = 32 h , register address: c h ) register : pa13 table2 [d h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa136 pa135 pa134 pa133 pa132 pa131 pa130 0 1 1 0 (initialization: pa13[6:0] = 36 h , register address: d h ) register : pa14 table2 [e h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa146 pa145 pa144 pa143 pa142 pa141 pa140 0 1 1 0 (initialization: pa14[6:0] = 3a h , register address: e h ) register : pa15 table2 [f h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa156 pa155 pa154 pa153 pa152 pa151 pa150 0 1 1 0 (initialization: pa15[6:0] = 3e h , register address: f h ) register : pa16 table3 [0 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa166 pa165 pa164 pa163 pa162 pa161 pa160 0 1 1 0 (initialization: pa16[6:0] = 42 h , register address: 0 h ) register : pa17 table3 [1 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa176 pa175 pa174 pa173 pa172 pa171 pa170 0 1 1 0 (initialization: pa17[6:0] = 46 h , register address: 1 h ) register : pa18 table3 [2 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa186 pa185 pa184 pa183 pa182 pa181 pa180 0 1 1 0 (initialization: pa18[6:0] = 4a h , register address: 2 h ) register : pa19 table3 [3 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa196 pa195 pa194 pa193 pa192 pa191 pa190 0 1 1 0 (initialization: pa19[6:0] = 4e h , register address: 3 h ) register : pa20 table3 [4 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa206 pa205 pa204 pa203 pa202 pa201 pa200 0 1 1 0 (initialization: pa20[6:0] = 52 h , register address: 4 h ) register : pa21 table3 [5 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa216 pa215 pa214 pa213 pa212 pa211 pa210 0 1 1 0 (initialization: pa21[6:0] = 56 h , register address: 5 h ) NJU6854 - 76 - ver.2004-06-29 register : pa22 table3 [6 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa226 pa225 pa224 pa223 pa222 pa221 pa220 0 1 1 0 (initialization: pa22[6:0] = 5a h , register address: 6 h ) register : pa23 table3 [7 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa236 pa235 pa234 pa233 pa232 pa231 pa230 0 1 1 0 (initialization: pa23[6:0] = 5e h , register address: 7 h ) register : pa24 table3 [8 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa246 pa245 pa244 pa243 pa242 pa241 pa240 0 1 1 0 (initialization: pa24[6:0] = 62 h , register address: 8 h ) register : pa25 table3 [9 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa256 pa255 pa254 pa253 pa252 pa251 pa250 0 1 1 0 (initialization: pa25[6:0] = 66 h , register address: 9 h ) register : pa26 table3 [a h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa266 pa265 pa264 pa263 pa262 pa261 pa260 0 1 1 0 (initialization: pa26[6:0] = 6a h , register address: a h ) register : pa27 table3 [b h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa276 pa275 pa274 pa273 pa272 pa271 pa270 0 1 1 0 (initialization: pa27[6:0] = 6e h , register address: b h ) register : pa28 table3 [c h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa286 pa285 pa284 pa283 pa282 pa281 pa280 0 1 1 0 (initialization: pa28[6:0] = 72 h , register address: c h ) register : pa29 table3 [d h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa296 pa295 pa294 pa293 pa292 pa291 pa290 0 1 1 0 (initialization: pa29[6:0] = 76 h , register address: d h ) register : pa30 table3 [e h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa306 pa305 pa304 pa303 pa302 pa301 pa300 0 1 1 0 (initialization: pa30[6:0] = 7a h , register address: e h ) register : pa31 table3 [f h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pa316 pa315 pa314 pa313 pa312 pa311 pa310 0 1 1 0 (initialization: pa31[6:0] = 7f h , register address: f h ) register : pb0 table4 [0 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb06 pb05 pb04 pb03 pb02 pb01 pb00 0 1 1 0 (initialization: pb0[6:0] = 0 h , register address: 0 h ) NJU6854 -77- ver.2004-06-29 register : pb1 table4 [1 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb16 pb15 pb14 pb13 pb12 pb11 pb10 0 1 1 0 (initialization: pb1[6:0] = 6 h , register address: 1 h ) register : pb2 table4 [2 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb26 pb25 pb24 pb23 pb22 pb21 pb20 0 1 1 0 (initialization: pb2[6:0] = a h , register address: 2 h ) register : pb3 table4 [3 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb36 pb35 pb34 pb33 pb32 pb31 pb30 0 1 1 0 (initialization: pb3[6:0] = e h , register address: 3 h ) register : pb4 table4 [4 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb46 pb45 pb44 pb43 pb42 pb41 pb40 0 1 1 0 (initialization: pb4[6:0] = 12 h , register address: 4 h ) register : pb5 table4 [5 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb56 pb55 pb54 pb53 pb52 pb51 pb50 0 1 1 0 (initialization: pb5[6:0] = 16 h , register address: 5 h ) register : pb6 table4 [6 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb66 pb65 pb64 pb63 pb62 pb61 pb60 0 1 1 0 (initialization: pb6[6:0] = 1a h , register address: 6 h ) register : pb7 table4 [7 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb76 pb75 pb74 pb73 pb72 pb71 pb70 0 1 1 0 (initialization: pb7[6:0] = 1e h , register address: 7 h ) register : pb8 table4 [8 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb86 pb85 pb84 pb83 pb82 pb81 pb80 0 1 1 0 (initialization: pb8[6:0] = 22 h , register address: 8 h ) register : pb9 table4 [9 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb96 pb95 pb94 pb93 pb92 pb91 pb90 0 1 1 0 (initialization: pb9[6:0] = 26 h , register address: 9 h ) register : pb10 table4 [a h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb106 pb105 pb104 pb103 pb102 pb101 pb100 0 1 1 0 (initialization: pb10[6:0] = 2a h , register address: a h ) register : pb11 table4 [b h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb116 pb115 pb114 pb113 pb112 pb111 pb110 0 1 1 0 (initialization: pb11[6:0] = 2e h , register address: b h ) register : pb12 table4 [c h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb126 pb125 pb124 pb123 pb122 pb121 pb120 0 1 1 0 (initialization: pb12[6:0] = 32 h , register address: c h ) NJU6854 - 78 - ver.2004-06-29 register : pb13 table4 [d h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb136 pb135 pb134 pb133 pb132 pb131 pb130 0 1 1 0 (initialization: pb13[6:0] = 36 h , register address: d h ) register : pb14 table4 [e h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb146 pb145 pb144 pb143 pb142 pb141 pb140 0 1 1 0 (initialization: pb14[6:0] = 3a h , register address: e h ) register : pb15 table4 [f h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb156 pb155 pb154 pb153 pb152 pb151 pb150 0 1 1 0 (initialization: pb15[6:0] = 3e h , register address: f h ) register : pb16 table5 [0 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb166 pb165 pb164 pb163 pb162 pb161 pb160 0 1 1 0 (initialization: pb16[6:0] = 42 h , register address: 0 h ) register : pb17 table5 [1 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb176 pb175 pb174 pb173 pb172 pb171 pb170 0 1 1 0 (initialization: pb17[6:0] = 46 h , register address: 1 h ) register : pb18 table5 [2 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb186 pb185 pb184 pb183 pb182 pb181 pb180 0 1 1 0 (initialization: pb18[6:0] = 4a h , register address: 2 h ) register : pb19 table5 [3 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb196 pb195 pb194 pb193 pb192 pb191 pb190 0 1 1 0 (initialization: pb19[6:0] = 4e h , register address: 3 h ) register : pb20 table5 [4 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb206 pb205 pb204 pb203 pb202 pb201 pb200 0 1 1 0 (initialization: pb20[6:0] = 52 h , register address: 4 h ) register : pb21 table5 [5 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb216 pb215 pb214 pb213 pb212 pb211 pb210 0 1 1 0 (initialization: pb21[6:0] = 56 h , register address: 5 h ) register : pb22 table5 [6 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb226 pb225 pb224 pb223 pb222 pb221 pb220 0 1 1 0 (initialization: pb22[6:0] = 5a h , register address: 6 h ) register : pb23 table5 [7 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb236 pb235 pb234 pb233 pb232 pb231 pb230 0 1 1 0 (initialization: pb23[6:0] = 5e h , register address: 7 h ) NJU6854 -79- ver.2004-06-29 register : pb24 table5 [8 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb246 pb245 pb244 pb243 pb242 pb241 pb240 0 1 1 0 (initialization: pb24[6:0] = 62 h , register address: 8 h ) register : pb25 table5 [9 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb256 pb255 pb254 pb253 pb252 pb251 pb250 0 1 1 0 (initialization: pb25[6:0] = 66 h , register address: 9 h ) register : pb26 table5 [a h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb266 pb265 pb264 pb263 pb262 pb261 pb260 0 1 1 0 (initialization: pb26[6:0] = 6a h , register address: a h ) register : pb27 table5 [b h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb276 pb275 pb274 pb273 pb272 pb271 pb270 0 1 1 0 (initialization: pb27[6:0] = 6e h , register address: b h ) register : pb28 table5 [c h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb286 pb285 pb284 pb283 pb282 pb281 pb280 0 1 1 0 (initialization: pb28[6:0] = 72 h , register address: c h ) register : pb29 table5 [d h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb296 pb295 pb294 pb293 pb292 pb291 pb290 0 1 1 0 (initialization: pb29[6:0] = 76 h , register address: d h ) register : pb30 table5 [e h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb306 pb305 pb304 pb303 pb302 pb301 pb300 0 1 1 0 (initialization: pb30[6:0] = 7a h , register address: e h ) register : pb31 table5 [f h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pb316 pb315 pb314 pb313 pb312 pb311 pb310 0 1 1 0 (initialization: pb31[6:0] = 7f h , register address: f h ) register : pc0 table6 [0 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc06 pc05 pc04 pc03 pc02 pc01 pc00 0 1 1 0 (initialization: pc0[6:0] = 0 h , register address: 0 h ) register : pc1 table6 [1 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc16 pc15 pc14 pc13 pc12 pc11 pc10 0 1 1 0 (initialization: pc1[6:0] = 6 h , register address: 1 h ) register : pc2 table6 [2 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc26 pc25 pc24 pc23 pc22 pc21 pc20 0 1 1 0 (initialization: pc2[6:0] = a h , register address: 2 h ) NJU6854 - 80 - ver.2004-06-29 register : pc3 table6 [3 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc36 pc35 pc34 pc33 pc32 pc31 pc30 0 1 1 0 (initialization: pc3[6:0] = e h , register address: 3 h ) register : pc4 table6 [4 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc46 pc45 pc44 pc43 pc42 pc41 pc40 0 1 1 0 (initialization: pc4[6:0] = 12 h , register address: 4 h ) register : pc5 table6 [5 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc56 pc55 pc54 pc53 pc52 pc51 pc50 0 1 1 0 (initialization: pc5[6:0] = 16 h , register address: 5 h ) register : pc6 table6 [6 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc66 pc65 pc64 pc63 pc62 pc61 pc60 0 1 1 0 (initialization: pc6[6:0] = 1a h , register address: 6 h ) register : pc7 table6 [7 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc76 pc75 pc74 pc73 pc72 pc71 pc70 0 1 1 0 (initialization: pc7[6:0] = 1e h , register address: 7 h ) register : pc8 table6 [8 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc86 pc85 pc84 pc83 pc82 pc81 pc80 0 1 1 0 (initialization: pc8[6:0] = 22 h , register address: 8 h ) register : pc9 table6 [9 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc96 pc95 pc94 pc93 pc92 pc91 pc90 0 1 1 0 (initialization: pc9[6:0] = 26 h , register address: 9 h ) register : pc10 table6 [a h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc106 pc105 pc104 pc103 pc102 pc101 pc100 0 1 1 0 (initialization: pc10[6:0] = 2a h , register address: a h ) register : pc11 table6 [b h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc116 pc115 pc114 pc113 pc112 pc111 pc110 0 1 1 0 (initialization: pc11[6:0] = 2e h , register address: b h ) register : pc12 table6 [c h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc126 pc125 pc124 pc123 pc122 pc121 pc120 0 1 1 0 (initialization: pc12[6:0] = 32 h , register address: c h ) register : pc13 table6 [d h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc136 pc135 pc134 pc133 pc132 pc131 pc130 0 1 1 0 (initialization: pc13[6:0] = 36 h , register address: d h ) register : pc14 table6 [e h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc146 pc145 pc144 pc143 pc142 pc141 pc140 0 1 1 0 (initialization: pc14[6:0] = 3a h , register address: e h ) NJU6854 -81- ver.2004-06-29 register : pc15 table6 [f h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc156 pc155 pc154 pc153 pc152 pc151 pc150 0 1 1 0 (initialization: pc15[6:0] = 3e h , register address: f h ) register : pc16 table7 [0 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc166 pc165 pc164 pc163 pc162 pc161 pc160 0 1 1 0 (initialization: pc16[6:0] = 42 h , register address: 0 h ) register : pc17 table7 [1 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc176 pc175 pc174 pc173 pc172 pc171 pc170 0 1 1 0 (initialization: pc17[6:0] = 46 h , register address: 1 h ) register : pc18 table7 [2 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc186 pc185 pc184 pc183 pc182 pc181 pc180 0 1 1 0 (initialization: pc18[6:0] = 4a h , register address: 2 h ) register : pc19 table7 [3 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc196 pc195 pc194 pc193 pc192 pc191 pc190 0 1 1 0 (initialization: pc19[6:0] = 4e h , register address: 3 h ) register : pc20 table7 [4 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc206 pc205 pc204 pc203 pc202 pc201 pc200 0 1 1 0 (initialization: pc20[6:0] = 52 h , register address: 4 h ) register : pc21 table7 [5 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc216 pc215 pc214 pc213 pc212 pc211 pc210 0 1 1 0 (initialization: pc21[6:0] = 56 h , register address: 5 h ) register : pc22 table7 [6 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc226 pc225 pc224 pc223 pc222 pc221 pc220 0 1 1 0 (initialization: pc22[6:0] = 5a h , register address: 6 h ) register : pc23 table7 [7 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc236 pc235 pc234 pc233 pc232 pc231 pc230 0 1 1 0 (initialization: pc23[6:0] = 5e h , register address: 7 h ) register : pc24 table7 [8 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc246 pc245 pc244 pc243 pc242 pc241 pc240 0 1 1 0 (initialization: pc24[6:0] = 62 h , register address: 8 h ) register : pc25 table7 [9 h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc256 pc255 pc254 pc253 pc252 pc251 pc250 0 1 1 0 (initialization: pc25[6:0] = 66 h , register address: 9 h ) NJU6854 - 82 - ver.2004-06-29 register : pc26 table7 [a h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc266 pc265 pc264 pc263 pc262 pc261 pc260 0 1 1 0 (initialization: pc26[6:0] = 6a h , register address: a h ) register : pc27 table7 [b h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc276 pc275 pc274 pc273 pc272 pc271 pc270 0 1 1 0 (initialization: pc27[6:0] = 6e h , register address: b h ) register : pc28 table7 [c h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc286 pc285 pc284 pc283 pc282 pc281 pc280 0 1 1 0 (initialization: pc28[6:0] = 72 h , register address: c h ) register : pc29 table7 [d h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc296 pc295 pc294 pc293 pc292 pc291 pc290 0 1 1 0 (initialization: pc29[6:0] = 76 h , register address: d h ) register : pc30 table7 [e h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc306 pc305 pc304 pc303 pc302 pc301 pc300 0 1 1 0 (initialization: pc30[6:0] = 7a h , register address: e h ) register : pc31 table8 [f h ] d7 d6 d5 d4 d3 d2 d1 d0 csb rs rdb wrb * pc316 pc315 pc314 pc313 pc312 pc311 pc310 0 1 1 0 (initialization: pc31[6:0] = 7f h , register address: f h ) NJU6854 -83- ver.2004-06-29 65k-color mode(32 grayscale from 128 levels, pwm1=1, pwm0=1) [three groups of palettes aj, bj and cj (j=0~31) are available] (marking points are default positions) palette grayscale level remarks (2) palette grayscale level remarks (2) 0 0 0 0 0 0 0 0/127 palette 0 initial value[6:0] 1 0 0 0 0 0 0 64/127 0 0 0 0 0 0 1 1/127 1 0 0 0 0 0 1 65/127 0 0 0 0 0 1 0 2/127 1 0 0 0 0 1 0 66/127 palette 16 initial value[6:0] 0 0 0 0 0 1 1 3/127 palette x initial value [6:0] (1) 1 0 0 0 0 1 1 67/127 0 0 0 0 1 0 0 4/127 1 0 0 0 1 0 0 68/127 0 0 0 0 1 0 1 5/127 1 0 0 0 1 0 1 69/127 0 0 0 0 1 1 0 6/127 palette 1 initial value[6:0] 1 0 0 0 1 1 0 70/127 palette 17 initial value[6:0] 0 0 0 0 1 1 1 7/127 1 0 0 0 1 1 1 71/127 0 0 0 1 0 0 0 8/127 1 0 0 1 0 0 0 72/127 0 0 0 1 0 0 1 9/127 1 0 0 1 0 0 1 73/127 0 0 0 1 0 1 0 10/127 palette 2 initial value[6:0] 1 0 0 1 0 1 0 74/127 palette 18 initial value[6:0] 0 0 0 1 0 1 1 11/127 1 0 0 1 0 1 1 75/127 0 0 0 1 1 0 0 12/127 1 0 0 1 1 0 0 76/127 0 0 0 1 1 0 1 13/127 1 0 0 1 1 0 1 77/127 0 0 0 1 1 1 0 14/127 palette 3 initial value[6:0] 1 0 0 1 1 1 0 78/127 palette 19 initial value[6:0] 0 0 0 1 1 1 1 15/127 1 0 0 1 1 1 1 79/127 0 0 1 0 0 0 0 16/127 1 0 1 0 0 0 0 80/127 0 0 1 0 0 0 1 17/127 1 0 1 0 0 0 1 81/127 0 0 1 0 0 1 0 18/127 palette 4 initial value[6:0] 1 0 1 0 0 1 0 82/127 palette 20 initial value[6:0] 0 0 1 0 0 1 1 19/127 1 0 1 0 0 1 1 83/127 0 0 1 0 1 0 0 20/127 1 0 1 0 1 0 0 84/127 0 0 1 0 1 0 1 21/127 1 0 1 0 1 0 1 85/127 0 0 1 0 1 1 0 22/127 palette 5 initial value[6:0] 1 0 1 0 1 1 0 86/127 palette 21 initial value[6:0] 0 0 1 0 1 1 1 23/127 1 0 1 0 1 1 1 87/127 0 0 1 1 0 0 0 24/127 1 0 1 1 0 0 0 88/127 0 0 1 1 0 0 1 25/127 1 0 1 1 0 0 1 89/127 0 0 1 1 0 1 0 26/127 palette 6 initial value[6:0] 1 0 1 1 0 1 0 90/127 palette 22 initial value[6:0] 0 0 1 1 0 1 1 27/127 1 0 1 1 0 1 1 91/127 0 0 1 1 1 0 0 28/127 1 0 1 1 1 0 0 92/127 0 0 1 1 1 0 1 29/127 1 0 1 1 1 0 1 93/127 0 0 1 1 1 1 0 30/127 palette 7 initial value[6:0] 1 0 1 1 1 1 0 94/127 palette 23 initial value[6:0] 0 0 1 1 1 1 1 31/127 1 0 1 1 1 1 1 95/127 0 1 0 0 0 0 0 32/127 1 1 0 0 0 0 0 96/127 0 1 0 0 0 0 1 33/127 1 1 0 0 0 0 1 97/127 0 1 0 0 0 1 0 34/127 palette 8 initial value[6:0] 1 1 0 0 0 1 0 98/127 palette 24 initial value[6:0] 0 1 0 0 0 1 1 35/127 1 1 0 0 0 1 1 99/127 0 1 0 0 1 0 0 36/127 1 1 0 0 1 0 0 100/127 0 1 0 0 1 0 1 37/127 1 1 0 0 1 0 1 101/127 0 1 0 0 1 1 0 38/127 palette 9 initial value[6:0] 1 1 0 0 1 1 0 102/127 palette 25 initial value[6:0] 0 1 0 0 1 1 1 39/127 1 1 0 0 1 1 1 103/127 0 1 0 1 0 0 0 40/127 1 1 0 1 0 0 0 104/127 0 1 0 1 0 0 1 41/127 1 1 0 1 0 0 1 105/127 0 1 0 1 0 1 0 42/127 palette 10 initial value[6:0] 1 1 0 1 0 1 0 106/127 palette 26 initial value[6:0] 0 1 0 1 0 1 1 43/127 1 1 0 1 0 1 1 107/127 0 1 0 1 1 0 0 44/127 1 1 0 1 1 0 0 108/127 0 1 0 1 1 0 1 45/127 1 1 0 1 1 0 1 109/127 0 1 0 1 1 1 0 46/127 palette 11 initial value[6:0] 1 1 0 1 1 1 0 110/127 palette 27 initial value[6:0] 0 1 0 1 1 1 1 47/127 1 1 0 1 1 1 1 111/127 0 1 1 0 0 0 0 48/127 1 1 1 0 0 0 0 112/127 0 1 1 0 0 0 1 49/127 1 1 1 0 0 0 1 113/127 0 1 1 0 0 1 0 50/127 palette 12 initial value[6:0] 1 1 1 0 0 1 0 114/127 palette 28 initial value[6:0] 0 1 1 0 0 1 1 51/127 1 1 1 0 0 1 1 115/127 0 1 1 0 1 0 0 52/127 1 1 1 0 1 0 0 116/127 0 1 1 0 1 0 1 53/127 1 1 1 0 1 0 1 117/127 0 1 1 0 1 1 0 54/127 palette 13 initial value[6:0] 1 1 1 0 1 1 0 118/127 palette 29 initial value[6:0] 0 1 1 0 1 1 1 55/127 1 1 1 0 1 1 1 119/127 0 1 1 1 0 0 0 56/127 1 1 1 1 0 0 0 120/127 0 1 1 1 0 0 1 57/127 1 1 1 1 0 0 1 121/127 0 1 1 1 0 1 0 58/127 palette 14 initial value[6:0] 1 1 1 1 0 1 0 122/127 palette 30 initial value[6:0] 0 1 1 1 0 1 1 59/127 1 1 1 1 0 1 1 123/127 0 1 1 1 1 0 0 60/127 1 1 1 1 1 0 0 124/127 0 1 1 1 1 0 1 61/127 1 1 1 1 1 0 1 125/127 0 1 1 1 1 1 0 62/127 palette 15 initial value[6:0] 1 1 1 1 1 1 0 126/127 0 1 1 1 1 1 1 63/127 1 1 1 1 1 1 1 127/127 palette 31 initial value[6:0] remark 1) pbx[6:0] grayscale palette is enable under gs = ?0?(defaults) setting. remark 2) please refer to the description of setting range, effective bit and rule for each grayscale palettes NJU6854 - 84 - ver.2004-06-29 65k-color mode(32 grayscale from 64 levels, pwm1=0, pwm0=0) [three groups of palettes aj, bj and cj (j=0~31) are available] (marking points are default positions) palette grayscale level remarks palette grayscale level remarks 0 0 0 0 0 0 x 0/63 palette 0 initial value[6:1] 1 0 0 0 0 0 x 32/63 0 0 0 0 0 1 x 1/63 palette x initial value[6:1] 1 0 0 0 0 1 x 33/63 palette 16 initial value[6:1] 0 0 0 0 1 0 x 2/63 1 0 0 0 1 0 x 34/63 0 0 0 0 1 1 x 3/63 palette 1 initial value[6:1] 1 0 0 0 1 1 x 35/63 palette 17 initial value[6:1] 0 0 0 1 0 0 x 4/63 1 0 0 1 0 0 x 36/63 0 0 0 1 0 1 x 5/63 palette 2 initial value[6:1] 1 0 0 1 0 1 x 37/63 palette 18 initial value[6:1] 0 0 0 1 1 0 x 6/63 1 0 0 1 1 0 x 38/63 0 0 0 1 1 1 x 7/63 palette 3 initial value[6:1] 1 0 0 1 1 1 x 39/63 palette 19 initial value[6:1] 0 0 1 0 0 0 x 8/63 1 0 1 0 0 0 x 40/63 0 0 1 0 0 1 x 9/63 palette 4 initial value[6:1] 1 0 1 0 0 1 x 41/63 palette 20 initial value[6:1] 0 0 1 0 1 0 x 10/63 1 0 1 0 1 0 x 42/63 0 0 1 0 1 1 x 11/63 palette 5 initial value[6:1] 1 0 1 0 1 1 x 43/63 palette 21 initial value[6:1] 0 0 1 1 0 0 x 12/63 1 0 1 1 0 0 x 44/63 0 0 1 1 0 1 x 13/63 palette 6 initial value[6:1] 1 0 1 1 0 1 x 45/63 palette 22 initial value[6:1] 0 0 1 1 1 0 x 14/63 1 0 1 1 1 0 x 46/63 0 0 1 1 1 1 x 15/63 palette 7 initial value[6:1] 1 0 1 1 1 1 x 47/63 palette 23 initial value[6:1] 0 1 0 0 0 0 x 16/63 1 1 0 0 0 0 x 48/63 0 1 0 0 0 1 x 17/63 palette 8 initial value[6:1] 1 1 0 0 0 1 x 49/63 palette 24 initial value[6:1] 0 1 0 0 1 0 x 18/63 1 1 0 0 1 0 x 50/63 0 1 0 0 1 1 x 19/63 palette 9 initial value[6:1] 1 1 0 0 1 1 x 51/63 palette 25 initial value[6:1] 0 1 0 1 0 0 x 20/63 1 1 0 1 0 0 x 52/63 0 1 0 1 0 1 x 21/63 palette 10 initial value[6:1] 1 1 0 1 0 1 x 53/63 palette 26 initial value[6:1] 0 1 0 1 1 0 x 22/63 1 1 0 1 1 0 x 54/63 0 1 0 1 1 1 x 23/63 palette 11 initial value[6:1] 1 1 0 1 1 1 x 55/63 palette 27 initial value[6:1] 0 1 1 0 0 0 x 24/63 1 1 1 0 0 0 x 56/63 0 1 1 0 0 1 x 25/63 palette 12 initial value[6:1] 1 1 1 0 0 1 x 57/63 palette 28 initial value][6:1] 0 1 1 0 1 0 x 26/63 1 1 1 0 1 0 x 58/63 0 1 1 0 1 1 x 27/63 palette 13 initial value[6:1] 1 1 1 0 1 1 x 59/63 palette 29 initial value[6:1] 0 1 1 1 0 0 x 28/63 1 1 1 1 0 0 x 60/63 0 1 1 1 0 1 x 29/63 palette 14 initial value[6:1] 1 1 1 1 0 1 x 61/63 palette 30 initial value[6:1] 0 1 1 1 1 0 x 30/63 1 1 1 1 1 0 x 62/63 0 1 1 1 1 1 x 31/63 palette 15 initial value[6:1] 1 1 1 1 1 1 x 63/63 palette 31 initial value[6:1] 65k-color mode(32 grayscale from 32 levels, pwm1=0, pwm0=1) [three groups of palettes aj, bj and cj (j=0~31) are available] (marking points are default positions) palette grayscale level remarks palette grayscale level remarks 0 0 0 0 0 x x 0/31 palette 0/x initial value[6:2] 1 0 0 0 0 x x 16/31 palette 16 initial value[6:2] 0 0 0 0 1 x x 1/31 palette 1 initial value[6:2] 1 0 0 0 1 x x 17/31 palette 17 initial value[6:2] 0 0 0 1 0 x x 2/31 palette 2 initial value[6:2] 1 0 0 1 0 x x 18/31 palette 18 initial value[6:2] 0 0 0 1 1 x x 3/31 palette 3 initial value[6:2] 1 0 0 1 1 x x 19/31 palette 19 initial value[6:2] 0 0 1 0 0 x x 4/31 palette 4 initial value[6:2] 1 0 1 0 0 x x 20/31 palette 20 initial value[6:2] 0 0 1 0 1 x x 5/31 palette 5 initial value[6:2] 1 0 1 0 1 x x 21/31 palette 21 initial value[6:2] 0 0 1 1 0 x x 6/31 palette 6 initial value[6:2] 1 0 1 1 0 x x 22/31 palette 22 initial value[6:2] 0 0 1 1 1 x x 7/31 palette 7 initial value[6:2] 1 0 1 1 1 x x 23/31 palette 23 initial value[6:2] 0 1 0 0 0 x x 8/31 palette 8 initial value[6:2] 1 1 0 0 0 x x 24/31 palette 24 initial value[6:2] 0 1 0 0 1 x x 9/31 palette 9 initial value[6:2] 1 1 0 0 1 x x 25/31 palette 25 initial value[6:2] 0 1 0 1 0 x x 10/31 palette 10 initial value[6:2] 1 1 0 1 0 x x 26/31 palette 26 initial value[6:2] 0 1 0 1 1 x x 11/31 palette 11 initial value[6:2] 1 1 0 1 1 x x 27/31 palette 27 initial value[6:2] 0 1 1 0 0 x x 12/31 palette 12 initial value[6:2] 1 1 1 0 0 x x 28/31 palette 28 initial value][6:2] 0 1 1 0 1 x x 13/31 palette 13 initial value[6:2] 1 1 1 0 1 x x 29/31 palette 29 initial value[6:2] 0 1 1 1 0 x x 14/31 palette 14 initial value[6:2] 1 1 1 1 0 x x 30/31 palette 30 initial value[6:2] 0 1 1 1 1 x x 15/31 palette 15 initial value[6:2] 1 1 1 1 1 x x 31/31 palette 31 initial value[6:2] NJU6854 -85- ver.2004-06-29 4k-color mode(16 grayscale from 128 levels, pwm1=1, pwm0=1) only odd number palettes ( ex palette1 palette3 .. palette31)are effective under 4k color mode. [three groups of palettes aj, bj and cj (j=1,3,5 ?29, 31) are available] (marking points are default positions) palette grayscale level remarks palette grayscale level remarks 0 0 0 0 0 0 0 0/127 1 0 0 0 0 0 0 64/127 0 0 0 0 0 0 1 1/127 1 0 0 0 0 0 1 65/127 0 0 0 0 0 1 0 2/127 1 0 0 0 0 1 0 66/127 0 0 0 0 0 1 1 3/127 1 0 0 0 0 1 1 67/127 0 0 0 0 1 0 0 4/127 1 0 0 0 1 0 0 68/127 0 0 0 0 1 0 1 5/127 1 0 0 0 1 0 1 69/127 0 0 0 0 1 1 0 6/127 palette 1 initial value[6:0] 1 0 0 0 1 1 0 70/127 palette 17 initial value[6:0] 0 0 0 0 1 1 1 7/127 1 0 0 0 1 1 1 71/127 0 0 0 1 0 0 0 8/127 1 0 0 1 0 0 0 72/127 0 0 0 1 0 0 1 9/127 1 0 0 1 0 0 1 73/127 0 0 0 1 0 1 0 10/127 1 0 0 1 0 1 0 74/127 0 0 0 1 0 1 1 11/127 1 0 0 1 0 1 1 75/127 0 0 0 1 1 0 0 12/127 1 0 0 1 1 0 0 76/127 0 0 0 1 1 0 1 13/127 1 0 0 1 1 0 1 77/127 0 0 0 1 1 1 0 14/127 palette 3 initial value[6:0] 1 0 0 1 1 1 0 78/127 palette 19 initial value[6:0] 0 0 0 1 1 1 1 15/127 1 0 0 1 1 1 1 79/127 0 0 1 0 0 0 0 16/127 1 0 1 0 0 0 0 80/127 0 0 1 0 0 0 1 17/127 1 0 1 0 0 0 1 81/127 0 0 1 0 0 1 0 18/127 1 0 1 0 0 1 0 82/127 0 0 1 0 0 1 1 19/127 1 0 1 0 0 1 1 83/127 0 0 1 0 1 0 0 20/127 1 0 1 0 1 0 0 84/127 0 0 1 0 1 0 1 21/127 1 0 1 0 1 0 1 85/127 0 0 1 0 1 1 0 22/127 palette 5 initial value[6:0] 1 0 1 0 1 1 0 86/127 palette 21 initial value[6:0] 0 0 1 0 1 1 1 23/127 1 0 1 0 1 1 1 87/127 0 0 1 1 0 0 0 24/127 1 0 1 1 0 0 0 88/127 0 0 1 1 0 0 1 25/127 1 0 1 1 0 0 1 89/127 0 0 1 1 0 1 0 26/127 1 0 1 1 0 1 0 90/127 0 0 1 1 0 1 1 27/127 1 0 1 1 0 1 1 91/127 0 0 1 1 1 0 0 28/127 1 0 1 1 1 0 0 92/127 0 0 1 1 1 0 1 29/127 1 0 1 1 1 0 1 93/127 0 0 1 1 1 1 0 30/127 palette 7 initial value[6:0] 1 0 1 1 1 1 0 94/127 palette 23 initial value[6:0] 0 0 1 1 1 1 1 31/127 1 0 1 1 1 1 1 95/127 0 1 0 0 0 0 0 32/127 1 1 0 0 0 0 0 96/127 0 1 0 0 0 0 1 33/127 1 1 0 0 0 0 1 97/127 0 1 0 0 0 1 0 34/127 1 1 0 0 0 1 0 98/127 0 1 0 0 0 1 1 35/127 1 1 0 0 0 1 1 99/127 0 1 0 0 1 0 0 36/127 1 1 0 0 1 0 0 100/127 0 1 0 0 1 0 1 37/127 1 1 0 0 1 0 1 101/127 0 1 0 0 1 1 0 38/127 palette 9 initial value[6:0] 1 1 0 0 1 1 0 102/127 palette 25 initial value[6:0] 0 1 0 0 1 1 1 39/127 1 1 0 0 1 1 1 103/127 0 1 0 1 0 0 0 40/127 1 1 0 1 0 0 0 104/127 0 1 0 1 0 0 1 41/127 1 1 0 1 0 0 1 105/127 0 1 0 1 0 1 0 42/127 1 1 0 1 0 1 0 106/127 0 1 0 1 0 1 1 43/127 1 1 0 1 0 1 1 107/127 0 1 0 1 1 0 0 44/127 1 1 0 1 1 0 0 108/127 0 1 0 1 1 0 1 45/127 1 1 0 1 1 0 1 109/127 0 1 0 1 1 1 0 46/127 palette 11 initial value[6:0] 1 1 0 1 1 1 0 110/127 palette 27 initial value[6:0] 0 1 0 1 1 1 1 47/127 1 1 0 1 1 1 1 111/127 0 1 1 0 0 0 0 48/127 1 1 1 0 0 0 0 112/127 0 1 1 0 0 0 1 49/127 1 1 1 0 0 0 1 113/127 0 1 1 0 0 1 0 50/127 1 1 1 0 0 1 0 114/127 0 1 1 0 0 1 1 51/127 1 1 1 0 0 1 1 115/127 0 1 1 0 1 0 0 52/127 1 1 1 0 1 0 0 116/127 0 1 1 0 1 0 1 53/127 1 1 1 0 1 0 1 117/127 0 1 1 0 1 1 0 54/127 palette 13 initial value[6:0] 1 1 1 0 1 1 0 118/127 palette 29 initial value[6:0] 0 1 1 0 1 1 1 55/127 1 1 1 0 1 1 1 119/127 0 1 1 1 0 0 0 56/127 1 1 1 1 0 0 0 120/127 0 1 1 1 0 0 1 57/127 1 1 1 1 0 0 1 121/127 0 1 1 1 0 1 0 58/127 1 1 1 1 0 1 0 122/127 0 1 1 1 0 1 1 59/127 1 1 1 1 0 1 1 123/127 0 1 1 1 1 0 0 60/127 1 1 1 1 1 0 0 124/127 0 1 1 1 1 0 1 61/127 1 1 1 1 1 0 1 125/127 0 1 1 1 1 1 0 62/127 palette 15 initial value[6:0] 1 1 1 1 1 1 0 126/127 0 1 1 1 1 1 1 63/127 1 1 1 1 1 1 1 127/127 palette 31 initial value[6:0] NJU6854 - 86 - ver.2004-06-29 4k-color mode(16 grayscale from 64 levels, pwm1=0, pwm0=0) [three groups of palettes aj, bj and cj (j=1,3,5 ?29, 31) are available] (marking points are default positions) palette grayscale level remarks palette grayscale level remarks 0 0 0 0 0 0 x 0/63 1 0 0 0 0 0 x 32/63 0 0 0 0 0 1 x 1/63 1 0 0 0 0 1 x 33/63 0 0 0 0 1 0 x 2/63 1 0 0 0 1 0 x 34/63 0 0 0 0 1 1 x 3/63 palette 1 initial value[6:1] 1 0 0 0 1 1 x 35/63 palette 17 initial value[6:1] 0 0 0 1 0 0 x 4/63 1 0 0 1 0 0 x 36/63 0 0 0 1 0 1 x 5/63 1 0 0 1 0 1 x 37/63 0 0 0 1 1 0 x 6/63 1 0 0 1 1 0 x 38/63 0 0 0 1 1 1 x 7/63 palette 3 initial value[6:1] 1 0 0 1 1 1 x 39/63 palette 19 initial value[6:1] 0 0 1 0 0 0 x 8/63 1 0 1 0 0 0 x 40/63 0 0 1 0 0 1 x 9/63 1 0 1 0 0 1 x 41/63 0 0 1 0 1 0 x 10/63 1 0 1 0 1 0 x 42/63 0 0 1 0 1 1 x 11/63 palette 5 initial value[6:1] 1 0 1 0 1 1 x 43/63 palette 21 initial value[6:1] 0 0 1 1 0 0 x 12/63 1 0 1 1 0 0 x 44/63 0 0 1 1 0 1 x 13/63 1 0 1 1 0 1 x 45/63 0 0 1 1 1 0 x 14/63 1 0 1 1 1 0 x 46/63 0 0 1 1 1 1 x 15/63 palette 7 initial value[6:1] 1 0 1 1 1 1 x 47/63 palette 23 initial value[6:1] 0 1 0 0 0 0 x 16/63 1 1 0 0 0 0 x 48/63 0 1 0 0 0 1 x 17/63 1 1 0 0 0 1 x 49/63 0 1 0 0 1 0 x 18/63 1 1 0 0 1 0 x 50/63 0 1 0 0 1 1 x 19/63 palette 9 initial value[6:1] 1 1 0 0 1 1 x 51/63 palette 25 initial value[6:1] 0 1 0 1 0 0 x 20/63 1 1 0 1 0 0 x 52/63 0 1 0 1 0 1 x 21/63 1 1 0 1 0 1 x 53/63 0 1 0 1 1 0 x 22/63 1 1 0 1 1 0 x 54/63 0 1 0 1 1 1 x 23/63 palette 11 initial value[6:1] 1 1 0 1 1 1 x 55/63 palette 27 initial value[6:1] 0 1 1 0 0 0 x 24/63 1 1 1 0 0 0 x 56/63 0 1 1 0 0 1 x 25/63 1 1 1 0 0 1 x 57/63 0 1 1 0 1 0 x 26/63 1 1 1 0 1 0 x 58/63 0 1 1 0 1 1 x 27/63 palette 13 initial value[6:1] 1 1 1 0 1 1 x 59/63 palette 29 initial value[6:1] 0 1 1 1 0 0 x 28/63 1 1 1 1 0 0 x 60/63 0 1 1 1 0 1 x 29/63 1 1 1 1 0 1 x 61/63 0 1 1 1 1 0 x 30/63 1 1 1 1 1 0 x 62/63 0 1 1 1 1 1 x 31/63 palette 15 initial value[6:1] 1 1 1 1 1 1 x 63/63 palette 31 initial value[6:1] 4k-color mode(16 grayscale from 32 levels, pwm1=0, pwm0=1) [three groups of palettes aj, bj and cj (j=1,3,5 ?29, 31) are available] (marking points are default positions) palette grayscale level remarks palette grayscale level remarks 0 0 0 0 0 x x 0/31 1 0 0 0 0 x x 16/31 0 0 0 0 1 x x 1/31 palette 1 initial value[6:2] 1 0 0 0 1 x x 17/31 palette 17 initial value[6:2] 0 0 0 1 0 x x 2/31 1 0 0 1 0 x x 18/31 0 0 0 1 1 x x 3/31 palette 3 initial value[6:2] 1 0 0 1 1 x x 19/31 palette 19 initial value[6:2] 0 0 1 0 0 x x 4/31 1 0 1 0 0 x x 20/31 0 0 1 0 1 x x 5/31 palette 5 initial value[6:2] 1 0 1 0 1 x x 21/31 palette 21 initial value[6:2] 0 0 1 1 0 x x 6/31 1 0 1 1 0 x x 22/31 0 0 1 1 1 x x 7/31 palette 7 initial value[6:2] 1 0 1 1 1 x x 23/31 palette 23 initial value[6:2] 0 1 0 0 0 x x 8/31 1 1 0 0 0 x x 24/31 0 1 0 0 1 x x 9/31 palette 9 initial value[6:2] 1 1 0 0 1 x x 25/31 palette 25 initial value[6:2] 0 1 0 1 0 x x 10/31 1 1 0 1 0 x x 26/31 0 1 0 1 1 x x 11/31 palette 11 initial value[6:2] 1 1 0 1 1 x x 27/31 palette 27 initial value[6:2] 0 1 1 0 0 x x 12/31 1 1 1 0 0 x x 28/31 0 1 1 0 1 x x 13/31 palette 13 initial value[6:2] 1 1 1 0 1 x x 29/31 palette 29 initial value[6:2] 0 1 1 1 0 x x 14/31 1 1 1 1 0 x x 30/31 0 1 1 1 1 x x 15/31 palette 15 initial value[6:2] 1 1 1 1 1 x x 31/31 palette 31 initial value[6:2] 4k-color mode(16 grayscale from 16 levels, pwm1=1, pwm0=0) [three groups of palettes aj, bj and cj (j=1,3,5 ?29, 31) are available] (marking points are default positions) palette grayscale level remarks palette grayscale level remarks 0 0 0 0 x x x 0/15 palette 1 initial value[6:3] 1 0 0 0 x x x 8/15 palette 17 initial value[6:3] 0 0 0 1 x x x 1/15 palette 3 initial value[6:3] 1 0 0 1 x x x 9/15 palette 19 initial value[6:3] 0 0 1 0 x x x 2/15 palette 5 initial value[6:3] 1 0 1 0 x x x 10/15 palette 21 initial value[6:3] 0 0 1 1 x x x 3/15 palette 7 initial value[6:3] 1 0 1 1 x x x 11/15 palette 23 initial value[6:3] 0 1 0 0 x x x 4/15 palette 9 initial value[6:3] 1 1 0 0 x x x 12/15 palette 25 initial value[6:3] 0 1 0 1 x x x 5/15 palette 11 initial value[6:3] 1 1 0 1 x x x 13/15 palette 27 initial value[6:3] 0 1 1 0 x x x 6/15 palette 13 initial value[6:3] 1 1 1 0 x x x 14/15 palette 29 initial value[6:3] 0 1 1 1 x x x 7/15 palette 15 initial value[6:3] 1 1 1 1 x x x 15/15 palette 31 initial value[6:3] NJU6854 -87- ver.2004-06-29 the setting range of the palette level which can be set up is limited in each palette (rgb common). level palette register palette selection range hex dec p6 p5 p4 p3 p2 p1 p0 0 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 2 2 0 0 0 0 0 1 0 3 3 0 0 0 0 0 1 1 4 4 0 0 0 0 1 0 0 5 5 0 0 0 0 1 0 1 6 6 0 0 0 0 1 1 0 7 7 0 0 0 0 1 1 1 8 8 0 0 0 1 0 0 0 9 9 0 0 0 1 0 0 1 a 10 0 0 0 1 0 1 0 b 11 0 0 0 1 0 1 1 c 12 0 0 0 1 1 0 0 d 13 0 0 0 1 1 0 1 e 14 0 0 0 1 1 1 0 f 15 0 0 0 1 1 1 1 10 16 0 0 1 0 0 0 0 11 17 0 0 1 0 0 0 1 12 18 0 0 1 0 0 1 0 13 19 0 0 1 0 0 1 1 14 20 0 0 1 0 1 0 0 15 21 0 0 1 0 1 0 1 16 22 0 0 1 0 1 1 0 17 23 0 0 1 0 1 1 1 18 24 0 0 1 1 0 0 0 19 25 0 0 1 1 0 0 1 1a 26 0 0 1 1 0 1 0 1b 27 0 0 1 1 0 1 1 1c 28 0 0 1 1 1 0 0 1d 29 0 0 1 1 1 0 1 1e 30 0 0 1 1 1 1 0 1f 31 0 0 1 1 1 1 1 20 32 0 1 0 0 0 0 0 21 33 0 1 0 0 0 0 1 22 34 0 1 0 0 0 1 0 23 35 0 1 0 0 0 1 1 24 36 0 1 0 0 1 0 0 25 37 0 1 0 0 1 0 1 26 38 0 1 0 0 1 1 0 27 39 0 1 0 0 1 1 1 28 40 0 1 0 1 0 0 0 29 41 0 1 0 1 0 0 1 2a 42 0 1 0 1 0 1 0 2b 43 0 1 0 1 0 1 1 2c 44 0 1 0 1 1 0 0 2d 45 0 1 0 1 1 0 1 2e 46 0 1 0 1 1 1 0 2f 47 0 1 0 1 1 1 1 30 48 0 1 1 0 0 0 0 31 49 0 1 1 0 0 0 1 32 50 0 1 1 0 0 1 0 33 51 0 1 1 0 0 1 1 34 52 0 1 1 0 1 0 0 35 53 0 1 1 0 1 0 1 36 54 0 1 1 0 1 1 0 37 55 0 1 1 0 1 1 1 38 56 0 1 1 1 0 0 0 39 57 0 1 1 1 0 0 1 3a 58 0 1 1 1 0 1 0 3b 59 0 1 1 1 0 1 1 3c 60 0 1 1 1 1 0 0 3d 61 0 1 1 1 1 0 1 3e 62 0 1 1 1 1 1 0 3f 63 0 1 1 1 1 1 1 40 64 1 0 0 0 0 0 0 41 65 1 0 0 0 0 0 1 42 66 1 0 0 0 0 1 0 43 67 1 0 0 0 0 1 1 44 68 1 0 0 0 1 0 0 45 69 1 0 0 0 1 0 1 46 70 1 0 0 0 1 1 0 47 71 1 0 0 0 1 1 1 48 72 1 0 0 1 0 0 0 49 73 1 0 0 1 0 0 1 4a 74 1 0 0 1 0 1 0 4b 75 1 0 0 1 0 1 1 4c 76 1 0 0 1 1 0 0 4d 77 1 0 0 1 1 0 1 4e 78 1 0 0 1 1 1 0 4f 79 1 0 0 1 1 1 1 50 80 1 0 1 0 0 0 0 51 81 1 0 1 0 0 0 1 52 82 1 0 1 0 0 1 0 53 83 1 0 1 0 0 1 1 54 84 1 0 1 0 1 0 0 55 85 1 0 1 0 1 0 1 56 86 1 0 1 0 1 1 0 57 87 1 0 1 0 1 1 1 58 88 1 0 1 1 0 0 0 59 89 1 0 1 1 0 0 1 5a 90 1 0 1 1 0 1 0 5b 91 1 0 1 1 0 1 1 5c 92 1 0 1 1 1 0 0 5d 93 1 0 1 1 1 0 1 5e 94 1 0 1 1 1 1 0 5f 95 1 0 1 1 1 1 1 60 96 1 1 0 0 0 0 0 61 97 1 1 0 0 0 0 1 62 98 1 1 0 0 0 1 0 63 99 1 1 0 0 0 1 1 64 100 1 1 0 0 1 0 0 65 101 1 1 0 0 1 0 1 66 102 1 1 0 0 1 1 0 67 103 1 1 0 0 1 1 1 68 104 1 1 0 1 0 0 0 69 105 1 1 0 1 0 0 1 6a 106 1 1 0 1 0 1 0 6b 107 1 1 0 1 0 1 1 6c 108 1 1 0 1 1 0 0 6d 109 1 1 0 1 1 0 1 6e 110 1 1 0 1 1 1 0 6f 111 1 1 0 1 1 1 1 70 112 1 1 1 0 0 0 0 71 113 1 1 1 0 0 0 1 72 114 1 1 1 0 0 1 0 73 115 1 1 1 0 0 1 1 74 116 1 1 1 0 1 0 0 75 117 1 1 1 0 1 0 1 76 118 1 1 1 0 1 1 0 77 119 1 1 1 0 1 1 1 78 120 1 1 1 1 0 0 0 79 121 1 1 1 1 0 0 1 7a 122 1 1 1 1 0 1 0 7b 123 1 1 1 1 0 1 1 7c 124 1 1 1 1 1 0 0 7d 125 1 1 1 1 1 0 1 7e 126 1 1 1 1 1 1 0 7f 127 1 1 1 1 1 1 1 caution: do not set same level for each gra yscale palette ( palette m = palette n ,m = 0 ~ 31, n = 0 ~ 31) forbidden random level palette ( palette n > palette n+1 ) NJU6854 - 88 - ver.2004-06-29 the setting range of the palette level can be expressed as the following table. palette register msb lsb palette no. 6 5 4 3 2 1 0 0 0 anything x 0 anything 1 0 anything 2 0 anything 3 0 anything 4 except(1,1) anything 5 except(1,1) anything 6 except(1,1) anything 7 except(1,1) anything 8 anything 9 anything 10 anything 11 anything 12 anything 13 anything 14 anything 15 anything 16 except(0,0) anything 17 except(0,0) anything 18 except(0,0) anything 19 except(0,0) anything 20 except(0,0) anything 21 except(0,0) anything 22 except(0,0) anything 23 except(0,0) anything 24 1 anything 25 1 anything 26 1 anything 27 1 anything 28 1 anything 29 1 anything 30 1 anything 31 1 anything caution: (1) do not set the same grayscale level in each grayscale palette(forbidden case: palette m = palette m+n , m=0~31 n=0~31) (2) do not set the zigzag typed grayscale palette. (forbidden case: palette n > palette n+1 , n=0~31 ) NJU6854 -89- ver.2004-06-29 (13) partial display function partial display function is used to save power. in the partial display mode, only specified common drivers output scanning signals, therefore part of the panel area is selected for display. because the duty ratio and lcd driving voltage are lowed in partial display mode. current consumption can be minimized. NJU6854 can realize 3 partial display areas on the screen once. the setting of partial display function is conducted through scan start com 1~3(ssc1~3) registers, partial display line number 1~3(pcc1~3) registers, power control 1~2 (tcbi,pow2) registers, amplifier gain/booster level(gvu) register, and 3 partial display/led control/rev (econt) register. refer to (15)typical instruction sequences for the functions setting the image of partial display. note) for the full screen display, set the scan start com 1(scc1) and the display line number(vpc). for the partial display, set the scan start com 1~3(scc1~3) and the partial display line number 1~3(pcc1~3). in this case, the partial display line number 1~3(pcc1~3) have priority over the display line number(vpc), and thus the display duty is: duty=pcc1+pcc2+pcc. (i) full screen display ssc1 (scan start com1) (ii) partial display (1 area) (iii) partial display (2 areas) (iv) partial display (3 areas) ssc1 (scan start com1) ssc1 (scan start com1) ssc2 (scan start com 2) ssc1 (scan start com1) ssc2 (scan start com 2) ssc3 (scan start com 3) vpc(display line number) vpc(display line number) vpc(display line number) vpc(display line number) pcc1(partial display line number 1) pcc1(partial display line number 1) pcc2(partial display line number 2) pcc1(partial display line number 1) pcc2(partial display line number 2) pcc3(partial display line number 3) (i) full screen display ssc1 (scan start com1) (ii) partial display (1 area) (iii) partial display (2 areas) (iv) partial display (3 areas) ssc1 (scan start com1) ssc1 (scan start com1) ssc2 (scan start com 2) ssc1 (scan start com1) ssc2 (scan start com 2) ssc3 (scan start com 3) vpc(display line number) vpc(display line number) vpc(display line number) vpc(display line number) pcc1(partial display line number 1) pcc1(partial display line number 1) pcc2(partial display line number 2) pcc1(partial display line number 1) pcc2(partial display line number 2) pcc3(partial display line number 3) NJU6854 - 90 - ver.2004-06-29 (14) relationship between logical com number and physical common driver (en3ptl=?0?) a b abababababababab coma0 comb0 -- -- coma1 comb1 -- -- coma2 comb2 -- -- coma3 comb3 -- -- coma4 comb4 -- -- coma5 comb5 -- -- coma6 comb6 -- -- coma7 comb7 -- -- coma8 comb8 -- -- coma9 comb9 -- -- coma10 comb10 - - - - coma11 comb11 - - - - coma12 comb12 - - - - coma13 comb13 0 53 0 53 96 43 17 105 52 105 52 9 62 17 coma14 comb14 1 54 1 54 97 44 18 104 51 104 51 8 61 16 coma15 comb15 2 55 2 55 98 45 19 103 50 103 50 7 60 15 coma16 comb16 3 56 3 56 99 46 102 49 102 49 6 59 coma17 comb17 4 57 4 57 100 47 101 48 101 48 5 58 coma18 comb18 5 58 5 58 101 48 100 47 100 47 4 57 coma19 comb19 6 59 6 59 102 49 99 46 99 46 3 56 coma20 comb20 7 60 7 60 103 50 98 45 98 45 2 55 coma21 comb21 8 61 8 61 104 51 97 44 97 44 1 54 coma22 comb22 9 62 9 62 105 52 96 43 96 43 0 53 coma23 comb23 10 63 10 63 0 53 95 42 95 42 105 52 coma24 comb24 11 64 11 64 1 54 94 41 94 41 104 51 coma25 comb25 12 65 12 65 2 55 93 40 93 40 103 50 coma26 comb26 13 66 13 66 3 56 92 39 92 39 102 49 coma27 comb27 14 67 14 67 4 57 91 38 91 38 101 48 coma28 comb28 15 68 15 68 5 58 90 37 90 37 100 47 coma29 comb29 16 69 16 69 6 59 89 36 89 36 99 46 coma30 comb30 17 70 17 70 7 60 88 35 88 35 98 45 coma31 comb31 18 71 18 71 8 61 87 34 87 34 97 44 coma32 comb32 19 72 19 72 9 62 86 33 86 33 96 43 coma33 comb33 20 73 20 73 10 63 85 32 85 32 95 42 coma34 comb34 21 74 21 74 11 64 84 31 84 31 94 41 coma35 comb35 22 75 22 75 12 65 83 30 83 30 93 40 coma36 comb36 23 76 23 76 13 66 82 29 82 29 92 39 coma37 comb37 24 77 24 77 14 67 81 28 81 28 91 38 coma38 comb38 25 78 25 78 15 68 80 27 80 27 90 37 coma39 comb39 26 79 26 79 16 69 79 26 79 26 89 36 coma40 comb40 27 80 27 80 17 70 20 78 25 78 25 88 35 14 coma41 comb41 28 81 28 81 18 71 21 77 24 77 24 87 34 13 coma42 comb42 29 82 29 82 19 72 22 76 23 76 23 86 33 12 coma43 comb43 30 83 30 83 20 73 23 75 22 75 22 85 32 11 coma44 comb44 31 84 31 84 21 74 24 74 21 74 21 84 31 10 coma45 comb45 32 85 32 85 22 75 25 73 20 73 20 83 30 9 coma46 comb46 33 86 33 86 23 76 26 72 19 72 19 82 29 8 coma47 comb47 34 87 34 87 24 77 27 71 18 71 18 81 28 7 coma48 comb48 35 88 35 88 25 78 28 70 17 70 17 80 27 6 coma49 comb49 36 89 36 89 26 79 0 29 69 16 69 16 79 26 34 5 coma50 comb50 37 90 37 90 27 80 1 30 68 15 68 15 78 25 33 4 coma51 comb51 38 91 38 91 28 81 2 31 67 14 67 14 77 24 32 3 coma52 comb52 39 92 39 92 29 82 3 32 66 13 66 13 76 23 31 2 coma53 comb53 40 93 40 93 30 83 4 33 65 12 65 12 75 22 30 1 coma54 comb54 41 94 41 94 31 84 5 34 64 11 64 11 74 21 29 0 coma55 comb55 42 95 42 95 32 85 6 63 10 63 10 73 20 28 coma56 comb56 43 96 43 96 33 86 7 62 9 62 9 72 19 27 coma57 comb57 44 97 44 97 34 87 8 61 8 61 8 71 18 26 coma58 comb58 45 98 45 98 35 88 9 60 7 60 7 70 17 25 coma59 comb59 46 99 46 99 36 89 10 59 6 59 6 69 16 24 coma60 comb60 47 100 47 100 37 90 11 58 5 58 5 68 15 23 coma61 comb61 48 101 48 101 38 91 12 57 4 57 4 67 14 22 coma62 comb62 49 102 49 102 39 92 13 56 3 56 3 66 13 21 coma63 comb63 50 103 50 103 40 93 14 55 2 55 2 65 12 20 coma64 comb64 51 104 51 104 41 94 15 54 1 54 1 64 11 19 coma65 comb65 52 105 52 105 42 95 16 53 0 53 0 63 10 18 (a <- b) one area one area two area reversed (a -> b) one area one area two area normal * *** *** *** 15 0015 0020 00 number ** 09611 0080 0050 10 36 logical com 020 0 0 logical com number ?0? (a start-> a end -> b start -> b end) ?0? ?1? 106 13 vpc (display line number) hct (header com) shift[1] (com shift a/b set) shift[0] (com shift direction) ssc3 (scan start com 3) pcc3 (line no. of partial display 3) r e m a r k ssc1 (scan start com 1) ssc2 (scan start com 2) pcc1 (line no. of partial display 1) pcc2 (line no. of partial display 2) physical com name NJU6854 -91- ver.2004-06-29 (en3ptl= ?1?) a b abababababababab coma0 comb0 -- -- coma1 comb1 -- -- coma2 comb2 -- -- coma3 comb3 -- -- coma4 comb4 -- -- coma5 comb5 -- -- coma6 comb6 -- -- coma7 comb7 -- -- coma8 comb8 -- -- coma9 comb9 -- -- coma10 comb10 - - - - coma11 comb11 - - - - coma12 comb12 - - - - coma13 comb13 53 0 53 0 43 96 17 52 105 52 105 62 9 17 coma14 comb14 54 1 54 1 44 97 18 51 104 51 104 61 8 16 coma15 comb15 55 2 55 2 45 98 19 50 103 50 103 60 7 15 coma16 comb16 56 3 56 3 46 99 49 102 49 102 59 6 coma17 comb17 57 4 57 4 47 100 48 101 48 101 58 5 coma18 comb18 58 5 58 5 48 101 47 100 47 100 57 4 coma19 comb19 59 6 59 6 49 102 46 99 46 99 56 3 coma20 comb20 60 7 60 7 50 103 45 98 45 98 55 2 coma21 comb21 61 8 61 8 51 104 44 97 44 97 54 1 coma22 comb22 62 9 62 9 52 105 43 96 43 96 53 0 coma23 comb23 63 10 63 10 53 0 42 95 42 95 52 105 coma24 comb24 64 11 64 11 54 1 41 94 41 94 51 104 coma25 comb25 65 12 65 12 55 2 40 93 40 93 50 103 coma26 comb26 66 13 66 13 56 3 39 92 39 92 49 102 coma27 comb27 67 14 67 14 57 4 38 91 38 91 48 101 coma28 comb28 68 15 68 15 58 5 37 90 37 90 47 100 coma29 comb29 69 16 69 16 59 6 36 89 36 89 46 99 coma30 comb30 70 17 70 17 60 7 35 88 35 88 45 98 coma31 comb31 71 18 71 18 61 8 34 87 34 87 44 97 coma32 comb32 72 19 72 19 62 9 33 86 33 86 43 96 coma33 comb33 73 20 73 20 63 10 32 85 32 85 42 95 coma34 comb34 74 21 74 21 64 11 31 84 31 84 41 94 coma35 comb35 75 22 75 22 65 12 30 83 30 83 40 93 coma36 comb36 76 23 76 23 66 13 29 82 29 82 39 92 coma37 comb37 77 24 77 24 67 14 28 81 28 81 38 91 coma38 comb38 78 25 78 25 68 15 27 80 27 80 37 90 coma39 comb39 79 26 79 26 69 16 26 79 26 79 36 89 coma40 comb40 80 27 80 27 70 17 20 25 78 25 78 35 88 14 coma41 comb41 81 28 81 28 71 18 21 24 77 24 77 34 87 13 coma42 comb42 82 29 82 29 72 19 22 23 76 23 76 33 86 12 coma43 comb43 83 30 83 30 73 20 23 22 75 22 75 32 85 11 coma44 comb44 84 31 84 31 74 21 24 21 74 21 74 31 84 10 coma45 comb45 85 32 85 32 75 22 25 20 73 20 73 30 83 9 coma46 comb46 86 33 86 33 76 23 26 19 72 19 72 29 82 8 coma47 comb47 87 34 87 34 77 24 27 18 71 18 71 28 81 7 coma48 comb48 88 35 88 35 78 25 28 17 70 17 70 27 80 6 coma49 comb49 89 36 89 36 79 26 29 0 16 69 16 69 26 79 5 34 coma50 comb50 90 37 90 37 80 27 30 1 15 68 15 68 25 78 4 33 coma51 comb51 91 38 91 38 81 28 31 2 14 67 14 67 24 77 3 32 coma52 comb52 92 39 92 39 82 29 32 3 13 66 13 66 23 76 2 31 coma53 comb53 93 40 93 40 83 30 33 4 12 65 12 65 22 75 1 30 coma54 comb54 94 41 94 41 84 31 34 5 11 64 11 64 21 74 0 29 coma55 comb55 95 42 95 42 85 32 6 10 63 10 63 20 73 28 coma56 comb56 96 43 96 43 86 33 7 9 62 9 62 19 72 27 coma57 comb57 97 44 97 44 87 34 8 8 61 8 61 18 71 26 coma58 comb58 98 45 98 45 88 35 9 7 60 7 60 17 70 25 coma59 comb59 99 46 99 46 89 36 10 6 59 6 59 16 69 24 coma60 comb60 100 47 100 47 90 37 11 5 58 5 58 15 68 23 coma61 comb61 101 48 101 48 91 38 12 4 57 4 57 14 67 22 coma62 comb62 102 49 102 49 92 39 13 3 56 3 56 13 66 21 coma63 comb63 103 50 103 50 93 40 14 2 55 2 55 12 65 20 coma64 comb64 104 51 104 51 94 41 15 1 54 1 54 11 64 19 coma65 comb65 105 52 105 52 95 42 16 0 53 0 53 10 63 18 (b <- a) one area one area two area reversed (b -> a) one area one area two area normal * *** *** 15 0015 0020 00 number *** ** 09611 0080 0050 10 36 logical com 020 0 0 logical com number ?1? (b start-> b end -> a start -> a end) ?0? ?1? 106 13 vpc (display line number) hct (header com) shift[1] (com shift a/b set) shift[0] (com shift direction) ssc3 (scan start com 3) pcc3 (line no. of partial display 3) r e m a r k ssc1 (scan start com 1) ssc2 (scan start com 2) pcc1 (line no. of partial display 1) pcc2 (line no. of partial display 2) physical com name NJU6854 - 92 - ver.2004-06-29 (en3ptl= ?1?) a b abababababababab coma0 comb0 - - - - coma1 comb1 - - - - coma2 comb2 - - - - coma3 comb3 - - - - coma4 comb4 - - - - coma5 comb5 - - - - coma6 comb6 - - - - coma7 comb7 - - - - coma8 comb8 - - - - coma9 comb9 - - - - coma10 comb10 - - - - coma11 comb11 - - - - coma12 comb12 - - - - coma13 comb13 0 53 0 53 96 43 17 105 52 105 52 9 62 22 coma14 comb14 1 54 1 54 97 44 18 104 51 104 51 8 61 21 coma15 comb15 2 55 2 55 98 45 19 103 50 103 50 7 60 20 coma16 comb16 3 56 3 56 99 46 102 49 102 49 6 59 coma17 comb17 4 57 4 57 100 47 101 48 101 48 5 58 coma18 comb18 5 58 5 58 101 48 100 47 100 47 4 57 coma19 comb19 6 59 6 59 102 49 99 46 99 46 3 56 coma20 comb20 7 60 7 60 103 50 98 45 98 45 2 55 coma21 comb21 8 61 8 61 104 51 97 44 97 44 1 54 coma22 comb22 9 62 9 62 105 52 96 43 96 43 0 53 coma23 comb23 10 63 10 63 0 53 95 42 95 42 105 52 coma24 comb24 11 64 11 64 1 54 94 41 94 41 104 51 coma25 comb25 12 65 12 65 2 55 93 40 93 40 103 50 coma26 comb26 13 66 13 66 3 56 92 39 92 39 102 49 coma27 comb27 14 67 14 67 4 57 91 38 91 38 101 48 coma28 comb28 15 68 15 68 5 58 90 37 90 37 100 47 coma29 comb29 16 69 16 69 6 59 89 36 89 36 99 46 coma30 comb30 17 70 17 70 7 60 88 35 88 35 98 45 coma31 comb31 18 71 18 71 8 61 87 34 87 34 97 44 coma32 comb32 19 72 19 72 9 62 86 33 86 33 96 43 coma33 comb33 20 73 20 73 10 63 85 32 85 32 95 42 coma34 comb34 21 74 21 74 11 64 84 31 84 31 94 41 coma35 comb35 22 75 22 75 12 65 83 30 83 30 93 40 coma36 comb36 23 76 23 76 13 66 82 29 82 29 92 39 coma37 comb37 24 77 24 77 14 67 81 28 81 28 91 38 coma38 comb38 25 78 25 78 15 68 80 27 80 27 90 37 coma39 comb39 26 79 26 79 16 69 79 26 79 26 89 36 coma40 comb40 27 80 27 80 17 70 20 78 25 78 25 88 35 19 coma41 comb41 28 81 28 81 18 71 21 77 24 77 24 87 34 18 coma42 comb42 29 82 29 82 19 72 22 76 23 76 23 86 33 17 coma43 comb43 30 83 30 83 20 73 23 75 22 75 22 85 32 16 coma44 comb44 31 84 31 84 21 74 24 74 21 74 21 84 31 15 coma45 comb45 32 85 32 85 22 75 25 73 20 73 20 83 30 14 coma46 comb46 33 86 33 86 23 76 26 72 19 72 19 82 29 13 coma47 comb47 34 87 34 87 24 77 27 71 18 71 18 81 28 12 coma48 comb48 35 88 35 88 25 78 28 70 17 70 17 80 27 11 coma49 comb49 36 89 36 89 26 79 0 29 69 16 69 16 79 26 39 10 coma50 comb50 37 90 37 90 27 80 1 30 68 15 68 15 78 25 38 9 coma51 comb51 38 91 38 91 28 81 2 31 67 14 67 14 77 24 37 8 coma52 comb52 39 92 39 92 29 82 3 32 66 13 66 13 76 23 36 7 coma53 comb53 40 93 40 93 30 83 4 33 65 12 65 12 75 22 35 6 coma54 comb54 41 94 41 94 31 84 5 34 64 11 64 11 74 21 34 5 coma55 comb55 42 95 42 95 32 85 6 63 10 63 10 73 20 33 coma56 comb56 43 96 43 96 33 86 7 62 9 62 9 72 19 32 coma57 comb57 44 97 44 97 34 87 8 61 8 61 8 71 18 31 coma58 comb58 45 98 45 98 35 88 9 60 7 60 7 70 17 30 coma59 comb59 46 99 46 99 36 89 10 59 6 59 6 69 16 29 coma60 comb60 47 100 47 100 37 90 11 58 5 58 5 68 15 28 coma61 comb61 48 101 48 101 38 91 12 35 57 4 57 4 67 14 27 4 coma62 comb62 49 102 49 102 39 92 13 36 56 3 56 3 66 13 26 3 coma63 comb63 50 103 50 103 40 93 14 37 55 2 55 2 65 12 25 2 coma64 comb64 51 104 51 104 41 94 15 38 54 1 54 1 64 11 24 1 coma65 comb65 52 105 52 105 42 95 16 39 53 0 53 0 63 10 23 0 (a <- b) one area one area two area reversed (a -> b) one area one area two area normal 50 005 0020 00101 5 0015 0015 00 number 00 0960 0080 0011 10 36 logical com 020 0 0 logical com number ?0? (a start-> a end -> b start -> b end) ?0? ?1? 106 13 vpc (display line number) hct (header com) shift[1] (com shift a/b set) shift[0] (com shift direction) ssc3 (scan start com 3) pcc3 (line no. of partial display 3) r e m a r k ssc1 (scan start com 1) ssc2 (scan start com 2) pcc1 (line no. of partial display 1) pcc2 (line no. of partial display 2) physical com name NJU6854 -93- ver.2004-06-29 (en3ptl= ?1?) a b abababababababab coma0 comb0 -- -- coma1 comb1 -- -- coma2 comb2 -- -- coma3 comb3 -- -- coma4 comb4 -- -- coma5 comb5 -- -- coma6 comb6 -- -- coma7 comb7 -- -- coma8 comb8 -- -- coma9 comb9 -- -- coma10 comb10 - - - - coma11 comb11 - - - - coma12 comb12 - - - - coma13 comb13 53 0 53 0 43 96 17 52 105 52 105 62 9 22 coma14 comb14 54 1 54 1 44 97 18 51 104 51 104 61 8 21 coma15 comb15 55 2 55 2 45 98 19 50 103 50 103 60 7 20 coma16 comb16 56 3 56 3 46 99 49 102 49 102 59 6 coma17 comb17 57 4 57 4 47 100 48 101 48 101 58 5 coma18 comb18 58 5 58 5 48 101 47 100 47 100 57 4 coma19 comb19 59 6 59 6 49 102 46 99 46 99 56 3 coma20 comb20 60 7 60 7 50 103 45 98 45 98 55 2 coma21 comb21 61 8 61 8 51 104 44 97 44 97 54 1 coma22 comb22 62 9 62 9 52 105 43 96 43 96 53 0 coma23 comb23 63 10 63 10 53 0 42 95 42 95 52 105 coma24 comb24 64 11 64 11 54 1 41 94 41 94 51 104 coma25 comb25 65 12 65 12 55 2 40 93 40 93 50 103 coma26 comb26 66 13 66 13 56 3 39 92 39 92 49 102 coma27 comb27 67 14 67 14 57 4 38 91 38 91 48 101 coma28 comb28 68 15 68 15 58 5 37 90 37 90 47 100 coma29 comb29 69 16 69 16 59 6 36 89 36 89 46 99 coma30 comb30 70 17 70 17 60 7 35 88 35 88 45 98 coma31 comb31 71 18 71 18 61 8 34 87 34 87 44 97 coma32 comb32 72 19 72 19 62 9 33 86 33 86 43 96 coma33 comb33 73 20 73 20 63 10 32 85 32 85 42 95 coma34 comb34 74 21 74 21 64 11 31 84 31 84 41 94 coma35 comb35 75 22 75 22 65 12 30 83 30 83 40 93 coma36 comb36 76 23 76 23 66 13 29 82 29 82 39 92 coma37 comb37 77 24 77 24 67 14 28 81 28 81 38 91 coma38 comb38 78 25 78 25 68 15 27 80 27 80 37 90 coma39 comb39 79 26 79 26 69 16 26 79 26 79 36 89 coma40 comb40 80 27 80 27 70 17 20 25 78 25 78 35 88 19 coma41 comb41 81 28 81 28 71 18 21 24 77 24 77 34 87 18 coma42 comb42 82 29 82 29 72 19 22 23 76 23 76 33 86 17 coma43 comb43 83 30 83 30 73 20 23 22 75 22 75 32 85 16 coma44 comb44 84 31 84 31 74 21 24 21 74 21 74 31 84 15 coma45 comb45 85 32 85 32 75 22 25 20 73 20 73 30 83 14 coma46 comb46 86 33 86 33 76 23 26 19 72 19 72 29 82 13 coma47 comb47 87 34 87 34 77 24 27 18 71 18 71 28 81 12 coma48 comb48 88 35 88 35 78 25 28 17 70 17 70 27 80 11 coma49 comb49 89 36 89 36 79 26 29 0 16 69 16 69 26 79 10 39 coma50 comb50 90 37 90 37 80 27 30 1 15 68 15 68 25 78 9 38 coma51 comb51 91 38 91 38 81 28 31 2 14 67 14 67 24 77 8 37 coma52 comb52 92 39 92 39 82 29 32 3 13 66 13 66 23 76 7 36 coma53 comb53 93 40 93 40 83 30 33 4 12 65 12 65 22 75 6 35 coma54 comb54 94 41 94 41 84 31 34 5 11 64 11 64 21 74 5 34 coma55 comb55 95 42 95 42 85 32 6 10 63 10 63 20 73 33 coma56 comb56 96 43 96 43 86 33 7 9 62 9 62 19 72 32 coma57 comb57 97 44 97 44 87 34 8 8 61 8 61 18 71 31 coma58 comb58 98 45 98 45 88 35 9 7 60 7 60 17 70 30 coma59 comb59 99 46 99 46 89 36 10 6 59 6 59 16 69 29 coma60 comb60 100 47 100 47 90 37 11 5 58 5 58 15 68 28 coma61 comb61 101 48 101 48 91 38 35 12 4 57 4 57 14 67 4 27 coma62 comb62 102 49 102 49 92 39 36 13 3 56 3 56 13 66 3 26 coma63 comb63 103 50 103 50 93 40 37 14 2 55 2 55 12 65 2 25 coma64 comb64 104 51 104 51 94 41 38 15 1 54 1 54 11 64 1 24 coma65 comb65 105 52 105 52 95 42 39 16 0 53 0 53 10 63 0 23 (b <- a) one area one area two area reversed (b -> a) one area one area two area normal 20 005 0010 5 0015 0015 00 number 00101 00 0960 0080 0011 10 36 logical com 020 0 0 logical com number ?1? (b start-> b end -> a start -> a end) ?0? ?1? 106 13 vpc (display line number) hct (header com) shift[1] (com shift a/b set) shift[0] (com shift direction) ssc3 (scan start com 3) pcc3 (line no. of partial display 3) r e m a r k ssc1 (scan start com 1) ssc2 (scan start com 2) pcc1 (line no. of partial display 1) pcc2 (line no. of partial display 2) physical com name NJU6854 - 94 - ver.2004-06-29 example of panel connection 1 (hct=00h) example of panel connection 2 (hct=0ah) shift[1:0] =(0,1) shift[1:0] =(0,0) comb[65~0] coma[0~65] scanning direction scanning direction panel physical com layout ram mapping 00h yaddress 83h 00h 83h x address shift[1:0] =(0,1) shift[1:0] =(0,0) comb[65~0] coma[0~65] scanning direction scanning direction panel physical com layout ram mapping 00h yaddress 83h 00h 83h x address shift[1:0] =(0,1) shift[1:0] =(0,0) comb[65~10] coma[10~65] scanning direction scanning direction panel physical com layout ram mapping 00h yaddress 83h 00h 83h x address 6fh 70h shift[1:0] =(0,1) shift[1:0] =(0,0) comb[65~10] coma[10~65] scanning direction scanning direction panel physical com layout ram mapping 00h yaddress 83h 00h 83h x address 6fh 70h NJU6854 -95- ver.2004-06-29 (15) typical instruction sequences (1) initialization (internal power supply) v dd , v ee ? v ss resb=?l? power supply stabilization resb=?h? wait display control duty ratio blank line number n-line inversion display mode power suppl y boost level, amplifier gain for v reg electronic volume bias ratio v reg , v ba power control (ckcont=?1", dcon=?1") wait end of initialization power suppl y power control (ampon=?1") note 1 ) if v ee is different from v dd , input v dd first note 2) waiting until v dd and v ee stabilization note 3) waiting at least 10 us note 4) waiting until v out stabilization note 5) waiting until v 0 and v 1 ~v 4 stabilization wait bus length selection 8 or 16-bit bus length selection NJU6854 - 96 - ver.2004-06-29 (2) initialization (external power supply) (3) data write (4) power off v dd on, resb=?l? power supply stabilization resb=?h? wait display control duty ratio blank line number n-line inversion display mode end of initialization note 1) waiting until v dd stabilization note 2) waiting at least 10 us note 3) waiting until v out , v 0 ~v 4 stabilization display data write display control initial display line display data configuration / window area x address y address display data on (on/off=?1") end of display data setting initialization function execute halt or reset instruction (all drivers outputs v ss ) execute discharge instruction (v 0 and v 1 ~v 4 capacitors discharge) wait v ee , v dd ~v ss off optional condition v out , v 0 ~v 4 on NJU6854 -97- ver.2004-06-29 (5) partial display optional condition dis p la y off ( on/off="0" ) internal power supply off ( dcon="0" , ampon="0" ) wait display control duty ratio initial display line partial display display on (on/off="1") power suppl y boost lever, amplifier gain of v reg electronic volume bias ratio v reg , v ba power control (dcon="1", ampon="1") partial display on wait note 1) waiting until voltage booster off note 2) waiting until v out stabilization note 3) waiting until v out v 0 and v 1 ~v 4 stabilization NJU6854 - 98 - ver.2004-06-29 absolute maximum ratings parameter symbol condition terminal rating unit supply voltage (1) v dd v dd -0.3 to +4.0 v supply voltage (2) v ee v ee -0.3 to +4.0 v supply voltage (3) v out v out -0.3 to +20.0 v supply voltage (4) v reg v reg -0.3 to +20.0 v supply voltage (5) v0 v0 -0.3 to +20.0 v supply voltage (6) v 1 , v 2 , v 3 , v 4 v 1 , v 2 , v 3 , v 4 -0.3 to v0 + 0.3 v input voltage v i v ss =0v ta = +25 c *1 -0.3 to v dd + 0.3 v storage temperature t stg -45 to +125 c note 1) d 0 ~ d 15 , csb, rs, rdb, wrb, osci, resb pins note 2) to stabilize the lsi operation, place decoupling capacitors between v dd and v ss , v ee and v ssh . recommended operating conditions parameter symbol terminal min typ max unit note v dd1 1.7 3.3 v *1 v dd2 v dd 2.4 3.3 v *2 supply voltage v ee v ee 2.4 3.3 v *3 v 0 v 0 5 18.0 v *4 v out v out 18.0 v v reg v reg v out 0.9 v operating voltage v ref v ref 1.59(tbd) 3.3 v *5 operating temperature t opr -30 85 c note1) applies to the condition when the reference voltage generator is not used. note2) applies to the condition when the reference voltage generator is used. note3) applies to the condition when the voltage booster is used. note4) the following relationship among the supply voltages must be maintained. v ssh NJU6854 - 100 - ver.2004-06-29 applicable pins and conditions *1 d 0 -d 15 , csb, rs, rdb, wrb, ps, sel68, resb *2 d 0 -d 15 *3 lp, flm, m *4 csb, rs, sel68, rdb, wrb, ps, resb, osci *5 d 0 -d 15 , m, flm, lp in the high impedance *6 sega 0 -sega 131 , segb 0 -segb 131 , segc 0 -segc 131 , coma 0 -coma 65 , comb 0 -comb 65 defines the resistance between the com/seg terminals and the power supply terminals (v 0 , v 1 , v 2 , v 3 and v 4 ) at the condition of 0.5v deference and 1/9 lcd bias ratio. *7 v dd the oscillator is halted, csb=?1? (disabled), no-load on the com/seg drivers *8 f osci - defines the internal oscillation frequency at (crf, crs1, crs0) = (0, 0, 0). f osc2 - defines the internal oscillation frequency at (crf, crs1, crs0) = (0, 0, 1). f osc3 - defines the internal oscillation frequency at (crf, crs1, crs0) = (1, 0, 0). f osc4 - defines the internal oscillation frequency at (crf, crs1, crs0) = (1, 0, 1). *9 f r1 - defines the internal oscillation frequency at (crf, crs1, crs0) = (0, 1, 0). *10 v out - n x boosting (n=2~6), applicable under internal oscillator circuit and internal power circuit are on state. - v ee =2.4v to 3.3v, evr= (1,1,1,1,1,1,1), 1/5 to 1/12 lcd bias, duty is 1/132 , no loads on com/seg drivers. - rl=500k ? between the v out and the v ss , ca 1 =ca 2 =1.0uf, ca 3 =0.1uf, dcon=?1?, ampon=?1? *11 v dd - applies to the condition using the internal oscillator and internal power circuits, no access between the lsi and mpu. evr value is ?1,1,1,1,1,1,1?. driving patterns are ?all pixels turned-on? or ?checkerboard? display in grayscale mode. no load are connected on the com/seg drivers. - v dd =v ee , v ref =0.9v ee , ca 1 =ca 2 =1.0uf, ca 3 =0.1uf, dcon=?1?, ampon=?1?, nlin=?0?, 1/132 duty cycle, ta=25 c *12 v ba v ee =2.4v to 3.3v , ta=25 c *13 v reg - v ee =2.4v to 3.3v, v ref =1.9(external)v, v out =18v, bias ratio is from 1/5 to 1/12, 1/132 duty cycle, evr=(1,1,1,1,1,1,1), checkerboard display, no-load on the com/seg drivers, the voltage booster n=2 to 6. ca 1 =ca 2 =1.0uf, ca 3 =0.1uf, dcon=?0?, ampon=?1?, nlin=?0? *14 v0, v 1 , v 2 , v 3 , v 4 - v ee =3.0v, v ref =0.9v ee , v out =15v, 1/5 to 1/12 lcd bias, evr= (1,1,1,1,1,1,1), display off, no-load on the com/seg drivers, voltage booster n=5. ca 1 =ca 2 =1.0uf, ca 3 =0.1uf, dcon=?0?, ampon=?1? v0 v1 v2 v3 v4 vss 1 2 3 4 vd12 = 1 - 2 vd34 = 3 - 4 vd24 = 2 - 4 (vd24 is applied to the condition that vd12 and vd34 are out o f specifications.) NJU6854 - 101 - ver.2004-06-29 ac characteristics (1) write operation (80-type mpu) (v dd =2.5 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlw8 t wrhw8 240 110 110 ns ns ns wrb data setup time data hold time t ds8 t dh8 60 15 ns ns d 0 to d 15 (v dd =1.7 to 2.5v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlw8 t wrhw8 300 95 95 ns ns ns wrb data setup time data hold time t ds8 t dh8 80 20 ns ns d 0 to d 15 note) each timing is specified based on 20% and 80% of v dd . t as8 csb wrb rs d 0 to d 15 t ah8 t wrlw8 t wrhw8 t ds8 t dh8 t cyc8 NJU6854 - 102 - ver.2004-06-29 (2) read operation (80-type mpu) (v dd =2.5 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlr8 t wrhr8 260 120 120 ns ns ns rdb read data delay time read data hold time t rdd8 t rdh8 cl=15pf 0 90 ns ns d 0 to d 15 (v dd =1.7 to 2.5v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlr8 t wrhr8 360 170 170 ns ns ns rdb read data delay time read data hold time t rdd8 t rdh8 cl=15pf 0 150 ns ns d 0 to d 15 note) each timing is specified based on 20% and 80% of v dd . t as8 csb rs d 0 to d 15 t rdd8 t rdh8 t cyc8 rdb t wrlr8 t wrhr8 t ah8 NJU6854 - 103 - ver.2004-06-29 (3) write operation (68-type mpu) (v dd =2.5 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elw6 t ehw6 240 110 110 ns ns ns e data setup time data hold time t ds6 t dh6 70 15 ns ns d 0 to d 15 (v dd =1.7 to 2.5v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elw6 t ehw6 300 95 95 ns ns ns e data setup time data hold time t ds6 t dh6 80 20 ns ns d 0 to d 15 note) each timing is specified based on 20% and 80% of v dd . t as6 csb rs t ah6 r/w ( wrb ) d 0 to d 15 t ehw 6 t elw6 t ds6 t dh6 t cyc6 e ( rdb ) NJU6854 - 104 - ver.2004-06-29 (4) read operation (68-type mpu) (v dd =2.5 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elr6 t ehr6 260 120 120 ns ns ns e read data delay time read data hold time t rdd6 t rdh6 cl=15pf 0 100 ns ns d 0 to d 15 (v dd =1.7 to 2.5v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elr6 t ehr6 360 170 170 ns ns ns e read data delay time read data hold time t rdd6 t rdh6 cl=15pf 0 150 ns ns d0 to d15 note) each timing is specified based on 20% and 80% of v dd . t as6 csb rs t ah6 r/w (wrb) d 0 to d 15 t ehr6 t elr6 t rdd6 t rdh6 t cyc6 e (rdb) NJU6854 - 105 - ver.2004-06-29 (5) serial interface (v dd =2.5 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal serial clock cycle scl ?h? level pulse width scl ?l? level pulse width t cycs t shw t slw tbd(75) tbd(33) tbd(33) ns ns ns scl address setup time address hold time t ass t ahs tbd(33) tbd(33) ns ns rs data setup time data hold time t dss t dhs tbd(33) tbd(33) ns ns sda csb ? scl time csb hold time t css t csh tbd(33) tbd(33) ns ns csb (v dd =1.7 to 2.5v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal serial clock cycle scl ?h? level pulse width scl ?l? level pulse width t cycs t shw t slw tbd(120) tbd(55) tbd(55) ns ns ns scl address setup time address hold time t ass t ahs tbd(55) tbd(55) ns ns rs data setup time data hold time t dss t dhs tbd(55) tbd(55) ns ns sda csb ? scl time csb hold time t css t csh tbd(55) tbd(55) ns ns csb note) each timing is specified based on 20% and 80% of v dd . t css csb rs t csh sda t slw t shw t dss t dhs t cycs scl t a hs t ass NJU6854 - 106 - ver.2004-06-29 (6) display control timing output timing (v dd =2.5 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal flm delay time t dflm 0 500 ns flm fr delay time t fr 0 500 ns fr cl delay time t dcl cl=15pf 0 200 ns cl output timing (v dd =1.7 to 2.5v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal flm delay time t dflm 0 1000 ns flm fr delay time t fr 0 1000 ns fr cl delay time t dcl cl=15pf 0 200 ns cl note) each timing is specified based on 20% and 80% of v dd . lp t dflm t m flm t dflm m osci t dlp NJU6854 - 107 - ver.2004-06-29 (7) reset input timing (v dd =2.4 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit te r m i n a l reset time t r 1.0 s resb ?l? level pulse width t rw 10.0 s resb (v dd =1.7 to 2.4v, ta=-30 to +85 c) parameter symbol condition min. max. unit te r m i n a l reset time t r 1.5 s resb ?l? level pulse width t rw 10.0 s resb note) each timing is specified based on 20% and 80% of v dd . t rw resb internal circuit status end of reset during reset t r t rw end of reset during reset t r t rw resb internal circuit status end of reset during reset t r t rw end of reset during reset t r NJU6854 - 108 - ver.2004-06-29 input/output block diagram parameter symbol min typ max unit basic delay time of gate ta=+25 c, v ss =0v, v dd =3.0v 10 ns i/o circuit types (a) input circuit vdd input signal input applicable pins : csb, rs rdb, wrb, sel68, p/s, resb, test, osci (b) output circuit vdd output signal output applicable pins : flm, lp, m, osco NJU6854 - 109 - ver.2004-06-29 (c) input/output circuit vdd input signal input/ output vdd output signal output control signal input control signal applicable pins : d0 ~ d15, (d) lcd drive circuit for graphic display vlcd output v1/v2 vlcd output control signal 1 output control signal 3 output control signal 2 output control signal 4 v3/v4 applicable pins : sega 0 to sega 1 31 segb 0 to segb 1 31 segc 0 to segc 1 31 com a 0 to com a 65 com b 0 to com b 65 NJU6854 - 110 - ver.2004-06-29 mpu connections 80-type mpu interface 68-type mpu interface serial interface a 1 ~a 7 a 0 v cc iorq d 0 ~d 7 rdb wrb resb csb rs d 0 ~d 7 rdb wrb resb v dd gnd v ss decoder reset input 8 7 1.7 v ~ 3.3 v NJU6854 80 series a 1 ~a 7 a 0 v cc iorq d 0 ~d 7 rs d 0 ~d 7 v dd v ss 7 NJU6854 80 a 1 ~a 7 a 0 v cc iorq d 0 ~d 7 rdb wrb resb csb rs d 0 ~d 7 rdb wrb resb v dd gnd v ss decoder reset input 8 7 1.7 v ~ 3.3 v NJU6854 80 series a 1 ~a 7 a 0 v cc iorq d 0 ~d 7 rs d 0 ~d 7 v dd v ss 7 NJU6854 80 a 1 ~a 15 a 0 v cc vma d 0 ~d 7 e wrb resb rs d 0 ~d 7 rdb(e) wrb(r/w) resb v dd gnd v ss decoder reset input 8 15 1.7 v ~ 3.3 v NJU6854 68 series a 1 ~a 15 a 0 v cc vma d 0 ~d 7 e wrb resb csb rs d 0 ~ 7 v dd gnd v ss decoder reset input 8 15 1.7 v ~ 3.3 v NJU6854 68 series a 1 ~a 15 a 0 v cc vma d 0 ~d 7 e wrb resb rs d 0 ~d 7 rdb(e) wrb(r/w) resb v dd gnd v ss decoder reset input 8 15 1.7 v ~ 3.3 v NJU6854 68 series a 1 ~a 15 a 0 v cc vma d 0 ~d 7 e wrb resb csb rs d 0 ~ 7 v dd gnd v ss decoder reset input 8 15 1.7 v ~ 3.3 v NJU6854 68 series a 1 ~a 7 a 0 v cc port 1 port 2 resb csb rs sda scl resb v dd gnd v ss decoder reset input 7 1.7 v ~ 3.3 v NJU6854 (cpu) a 1 ~a 7 a 0 v cc port 1 port 2 resb csb rs sda scl resb v dd gnd v ss decoder reset input 7 1.7 v ~ 3.3 v NJU6854 (cpu) a 1 ~a 7 a 0 v cc port 1 port 2 resb csb rs sda scl resb v dd gnd v ss decoder reset input 7 1.7 v ~ 3.3 v NJU6854 (cpu) a 1 ~a 7 a 0 v cc port 1 port 2 resb csb rs sda scl resb v dd gnd v ss decoder reset input 7 1.7 v ~ 3.3 v NJU6854 (cpu) NJU6854 - 111 - ver.2004-06-29 memo [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. |
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